[PATCH] D124096: [RISCV] Use default promotion for (i32 (shl 1, X)) on RV64 when Zbs is enabled.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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This improves opportunities to use bset/bclr/binv. Unfortunately,
there are no W versions of these instrcutions so this isn't always
a clear win. If we use SLLW we get free sign extend and shift masking,
but need to put a 1 in a register and can't remove an or/xor. If
we use bset/bclr/binv we remove the immediate materializationg and
logic op, but might need a mask on the shift amount and sext.w.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D124096

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rv64zbs.ll

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