[PATCH] D124089: [RISCV] Add a test showing incorrect VSETVLI insertion

[Fraser Cormack via Phabricator via llvm-commits]

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This test shows incorrect cross-bb insertion. We'd expect to see
a SEW=8 vsetvli, something like:

  vsetvli zero, zero, e8, mf8, ta, mu
  vluxei64.v      v1, (a2), v8, v0.t

But instead the vsetvli is omitted and instead an inherited SEW=64
vsetvli is used:

1. %bb.0: vmv1r.v v9, v1 vsetvli a3, zero, e64, m1, ta, mu vmseq.vi        v9, v1, 0 vmv1r.v v8, v0 vmandn.mm       v0, v9, v2 beqz    a0, .LBB0_2
2. %bb.1: vluxei64.v      v1, (a2), v8, v0.t vmv1r.v v3, v1

The "mask reg op" vmandn.mm in bb.1 appears to be confusing the insertion
process, as it is able to elide its own vsetvli as its VLMAX (SEW=8,
LMUL=MF8) is identical to the previous one (SEW=64, LMUL=1).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D124089

Files:
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir

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