[PATCH] D123910: [HWAsan] Fix the hard code on kernel page size bits

[Xiaodong Liu via Phabricator via llvm-commits]

XiaodongLoong updated this revision to Diff 423885.
XiaodongLoong edited the summary of this revision.
XiaodongLoong added a comment.

upate revision for refactor


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123910/new/

https://reviews.llvm.org/D123910

Files:
  llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp


Index: llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
===================================================================
--- llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
+++ llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
@@ -1263,13 +1263,14 @@
     // Update the ring buffer. Top byte of ThreadLong defines the size of the
     // buffer in pages, it must be a power of two, and the start of the buffer
     // must be aligned by twice that much. Therefore wrap around of the ring
-    // buffer is simply Addr &= ~((ThreadLong >> 56) << 12).
+    // buffer is simply Addr &= ~((ThreadLong >> 56) << SystemPageSizeBits).
     // The use of AShr instead of LShr is due to
     //   https://bugs.llvm.org/show_bug.cgi?id=39030
     // Runtime library makes sure not to use the highest bit.
-    Value *WrapMask = IRB.CreateXor(
-        IRB.CreateShl(IRB.CreateAShr(ThreadLong, 56), 12, "", true, true),
-        ConstantInt::get(IntptrTy, (uint64_t)-1));
+    Value *WrapMask =
+        IRB.CreateXor(IRB.CreateShl(IRB.CreateAShr(ThreadLong, 56),
+                                    getSystemPageSizeBits(), "", true, true),
+                      ConstantInt::get(IntptrTy, (uint64_t)-1));
     Value *ThreadLongNew = IRB.CreateAnd(
         IRB.CreateAdd(ThreadLong, ConstantInt::get(IntptrTy, 8)), WrapMask);
     IRB.CreateStore(ThreadLongNew, SlotPtr);


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