[llvm] 987df72 - AMDGPU: Serialize VGPRForAGPRCopy
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 19 19:25:21 PDT 2022
Author: Matt Arsenault
Date: 2022-04-19T22:14:52-04:00
New Revision: 987df725ac2b802a6e158e0c3012f6cf8c996f97
URL: https://github.com/llvm/llvm-project/commit/987df725ac2b802a6e158e0c3012f6cf8c996f97
DIFF: https://github.com/llvm/llvm-project/commit/987df725ac2b802a6e158e0c3012f6cf8c996f97.diff
LOG: AMDGPU: Serialize VGPRForAGPRCopy
Added:
llvm/test/CodeGen/MIR/AMDGPU/vgpr-for-agpr-copy-invalid-reg.mir
Modified:
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 0ab8bba527d22..8db5d63f290b1 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1417,6 +1417,14 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
return false;
};
+ auto parseOptionalRegister = [&](const yaml::StringValue &RegName,
+ Register &RegVal) {
+ return !RegName.Value.empty() && parseRegister(RegName, RegVal);
+ };
+
+ if (parseOptionalRegister(YamlMFI.VGPRForAGPRCopy, MFI->VGPRForAGPRCopy))
+ return true;
+
auto diagnoseRegisterClass = [&](const yaml::StringValue &RegName) {
// Create a diagnostic for a the register string literal.
const MemoryBuffer &Buffer =
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
index 121263c725bd9..682e24be2f1a0 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
@@ -590,6 +590,8 @@ yaml::SIMachineFunctionInfo::SIMachineFunctionInfo(
for (Register Reg : MFI.WWMReservedRegs)
WWMReservedRegs.push_back(regToString(Reg, TRI));
+ if (MFI.getVGPRForAGPRCopy())
+ VGPRForAGPRCopy = regToString(MFI.getVGPRForAGPRCopy(), TRI);
auto SFI = MFI.getOptionalScavengeFI();
if (SFI)
ScavengeFI = yaml::FrameIndex(*SFI, MF.getFrameInfo());
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
index ce28cc7bc9a41..22439804d5726 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
@@ -296,6 +296,7 @@ struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo {
Optional<SIArgumentInfo> ArgInfo;
SIMode Mode;
Optional<FrameIndex> ScavengeFI;
+ StringValue VGPRForAGPRCopy;
SIMachineFunctionInfo() = default;
SIMachineFunctionInfo(const llvm::SIMachineFunctionInfo &,
@@ -335,6 +336,8 @@ template <> struct MappingTraits<SIMachineFunctionInfo> {
YamlIO.mapOptional("occupancy", MFI.Occupancy, 0);
YamlIO.mapOptional("wwmReservedRegs", MFI.WWMReservedRegs);
YamlIO.mapOptional("scavengeFI", MFI.ScavengeFI);
+ YamlIO.mapOptional("vgprForAGPRCopy", MFI.VGPRForAGPRCopy,
+ StringValue()); // Don't print out when it's empty.
}
};
@@ -518,8 +521,6 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
public:
Register getVGPRForAGPRCopy() const {
- assert(VGPRForAGPRCopy &&
- "Valid VGPR for AGPR copy must have been identified by now");
return VGPRForAGPRCopy;
}
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
index 54b38a2981841..2f4a431401de1 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
+++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
@@ -36,6 +36,7 @@
; AFTER-PEI-NEXT: highBitsOf32BitAddress: 0
; AFTER-PEI-NEXT: occupancy: 5
; AFTER-PEI-NEXT: scavengeFI: '%fixed-stack.0'
+; AFTER-PEI-NEXT: vgprForAGPRCopy: ''
; AFTER-PEI-NEXT: body:
define amdgpu_kernel void @scavenge_fi(i32 addrspace(1)* %out, i32 %in) #0 {
%wide.sgpr0 = call <32 x i32> asm sideeffect "; def $0", "=s" () #0
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
index 995d908d0a2f8..082711ac2d6f5 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
@@ -44,6 +44,7 @@
# FULL-NEXT: fp64-fp16-output-denormals: true
# FULL-NEXT: highBitsOf32BitAddress: 0
# FULL-NEXT: occupancy: 10
+# FULL-NEXT: vgprForAGPRCopy: ''
# FULL-NEXT: body:
# SIMPLE: machineFunctionInfo:
@@ -139,6 +140,7 @@ body: |
# FULL-NEXT: fp64-fp16-output-denormals: true
# FULL-NEXT: highBitsOf32BitAddress: 0
# FULL-NEXT: occupancy: 10
+# FULL-NEXT: vgprForAGPRCopy: ''
# FULL-NEXT: body:
# SIMPLE: machineFunctionInfo:
@@ -205,6 +207,7 @@ body: |
# FULL-NEXT: fp64-fp16-output-denormals: true
# FULL-NEXT: highBitsOf32BitAddress: 0
# FULL-NEXT: occupancy: 10
+# FULL-NEXT: vgprForAGPRCopy: ''
# FULL-NEXT: body:
# SIMPLE: machineFunctionInfo:
@@ -272,6 +275,7 @@ body: |
# FULL-NEXT: fp64-fp16-output-denormals: true
# FULL-NEXT: highBitsOf32BitAddress: 0
# FULL-NEXT: occupancy: 10
+# FULL-NEXT: vgprForAGPRCopy: ''
# FULL-NEXT: body:
# SIMPLE: machineFunctionInfo:
@@ -491,3 +495,28 @@ body: |
SI_RETURN
...
+
+---
+# ALL-LABEL: name: vgpr_for_agpr_copy
+# ALL: vgprForAGPRCopy: '$vgpr2'
+name: vgpr_for_agpr_copy
+machineFunctionInfo:
+ vgprForAGPRCopy: '$vgpr2'
+body: |
+ bb.0:
+ SI_RETURN
+
+...
+
+---
+# ALL-LABEL: name: vgpr_for_agpr_copy_noreg
+# FULL: vgprForAGPRCopy: ''
+# SIMPLE-NOT: vgprForAGPRCopy
+name: vgpr_for_agpr_copy_noreg
+machineFunctionInfo:
+ vgprForAGPRCopy: '$noreg'
+body: |
+ bb.0:
+ SI_RETURN
+
+...
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
index a3c0e7b2850f5..c3dde88dcd746 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
+++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
@@ -39,6 +39,7 @@
; CHECK-NEXT: fp64-fp16-output-denormals: true
; CHECK-NEXT: highBitsOf32BitAddress: 0
; CHECK-NEXT: occupancy: 10
+; CHECK-NEXT: vgprForAGPRCopy: ''
; CHECK-NEXT: body:
define amdgpu_kernel void @kernel(i32 %arg0, i64 %arg1, <16 x i32> %arg2) {
%gep = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %arg0
@@ -78,6 +79,7 @@ define amdgpu_kernel void @kernel(i32 %arg0, i64 %arg1, <16 x i32> %arg2) {
; CHECK-NEXT: fp64-fp16-output-denormals: true
; CHECK-NEXT: highBitsOf32BitAddress: 0
; CHECK-NEXT: occupancy: 10
+; CHECK-NEXT: vgprForAGPRCopy: ''
; CHECK-NEXT: body:
define amdgpu_ps void @ps_shader(i32 %arg0, i32 inreg %arg1) {
%gep = getelementptr inbounds [128 x i32], [128 x i32] addrspace(2)* @gds, i32 0, i32 %arg0
@@ -130,6 +132,7 @@ define amdgpu_ps void @gds_size_shader(i32 %arg0, i32 inreg %arg1) #5 {
; CHECK-NEXT: fp64-fp16-output-denormals: true
; CHECK-NEXT: highBitsOf32BitAddress: 0
; CHECK-NEXT: occupancy: 10
+; CHECK-NEXT: vgprForAGPRCopy: ''
; CHECK-NEXT: body:
define void @function() {
ret void
@@ -174,6 +177,7 @@ define void @function() {
; CHECK-NEXT: fp64-fp16-output-denormals: true
; CHECK-NEXT: highBitsOf32BitAddress: 0
; CHECK-NEXT: occupancy: 10
+; CHECK-NEXT: vgprForAGPRCopy: ''
; CHECK-NEXT: body:
define void @function_nsz() #0 {
ret void
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/vgpr-for-agpr-copy-invalid-reg.mir b/llvm/test/CodeGen/MIR/AMDGPU/vgpr-for-agpr-copy-invalid-reg.mir
new file mode 100644
index 0000000000000..80f07e07569a3
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/AMDGPU/vgpr-for-agpr-copy-invalid-reg.mir
@@ -0,0 +1,12 @@
+# RUN: not llc -mtriple=amdgcn-amd-amdhsa -run-pass=none -verify-machineinstrs %s -o /dev/null 2>&1 | FileCheck -check-prefix=ERR %s
+
+---
+name: invalid_reg
+machineFunctionInfo:
+# ERR: [[@LINE+1]]:21: unknown register name 'arst'
+ vgprForAGPRCopy: '$arst'
+body: |
+ bb.0:
+ S_ENDPGM 0
+
+...
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