[llvm] b39d34d - AMDGPU: More mad_64_32 test cases for multiple uses
Nicolai Hähnle via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 19 16:00:25 PDT 2022
Author: Nicolai Hähnle
Date: 2022-04-19T18:00:05-05:00
New Revision: b39d34de5e6b05012989e96d83fd3267d74db4cb
URL: https://github.com/llvm/llvm-project/commit/b39d34de5e6b05012989e96d83fd3267d74db4cb
DIFF: https://github.com/llvm/llvm-project/commit/b39d34de5e6b05012989e96d83fd3267d74db4cb.diff
LOG: AMDGPU: More mad_64_32 test cases for multiple uses
Also use gfx90a for the gfx9 test, whose code gen should be affected by
faster multiply-add instructions.
Added:
Modified:
llvm/test/CodeGen/AMDGPU/mad_64_32.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/mad_64_32.ll b/llvm/test/CodeGen/AMDGPU/mad_64_32.ll
index e560ef63fdde3..abc40d734a7cc 100644
--- a/llvm/test/CodeGen/AMDGPU/mad_64_32.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad_64_32.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=CI %s
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=SI %s
-; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9 %s
+; RUN: llc -march=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9 %s
define i64 @mad_i64_i32_sextops(i32 %arg0, i32 %arg1, i64 %arg2) #0 {
; CI-LABEL: mad_i64_i32_sextops:
@@ -179,24 +179,26 @@ define i128 @mad_i64_i32_sextops_i32_i128(i32 %arg0, i32 %arg1, i128 %arg2) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v0, v1, 0
; GFX9-NEXT: v_ashrrev_i32_e32 v13, 31, v0
-; GFX9-NEXT: v_mov_b32_e32 v8, 0
-; GFX9-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v13, v1, v[7:8]
+; GFX9-NEXT: v_mov_b32_e32 v9, 0
+; GFX9-NEXT: v_mov_b32_e32 v8, v7
+; GFX9-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v13, v1, v[8:9]
; GFX9-NEXT: v_ashrrev_i32_e32 v14, 31, v1
-; GFX9-NEXT: v_mad_i64_i32 v[11:12], s[4:5], v1, v13, 0
-; GFX9-NEXT: v_mov_b32_e32 v7, v10
-; GFX9-NEXT: v_mov_b32_e32 v10, v8
-; GFX9-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v0, v14, v[9:10]
-; GFX9-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v14, v0, v[11:12]
-; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v7, v9
-; GFX9-NEXT: v_addc_co_u32_e64 v10, s[4:5], 0, 0, vcc
-; GFX9-NEXT: v_mad_u64_u32 v[9:10], s[4:5], v13, v14, v[9:10]
-; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v9, v0
-; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v10, v1, vcc
-; GFX9-NEXT: v_mov_b32_e32 v1, v8
+; GFX9-NEXT: v_mov_b32_e32 v8, v11
+; GFX9-NEXT: v_mov_b32_e32 v11, v9
+; GFX9-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v0, v14, v[10:11]
+; GFX9-NEXT: v_mov_b32_e32 v12, v11
+; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v8, v12
+; GFX9-NEXT: v_addc_co_u32_e64 v9, s[4:5], 0, 0, vcc
+; GFX9-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v13, v14, v[8:9]
+; GFX9-NEXT: v_mad_i64_i32 v[12:13], s[4:5], v1, v13, 0
+; GFX9-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v14, v0, v[12:13]
+; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v0
+; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v9, v1, vcc
+; GFX9-NEXT: v_mov_b32_e32 v1, v10
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v6, v2
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v4, vcc
-; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v9, v5, vcc
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v5, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
%sext0 = sext i32 %arg0 to i128
%sext1 = sext i32 %arg1 to i128
@@ -265,8 +267,8 @@ define i63 @mad_i64_i32_sextops_i31_i63(i31 %arg0, i31 %arg1, i63 %arg2) #0 {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_lshlrev_b64 v[2:3], 1, v[2:3]
-; GFX9-NEXT: v_bfe_i32 v1, v1, 0, 31
; GFX9-NEXT: v_ashrrev_i64 v[2:3], 1, v[2:3]
+; GFX9-NEXT: v_bfe_i32 v1, v1, 0, 31
; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 31
; GFX9-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v0, v1, v[2:3]
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -526,12 +528,11 @@ define amdgpu_kernel void @mad_i64_i32_uniform(i64 addrspace(1)* %out, i32 %arg0
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2c
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[0:1], 0x24
-; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v2, s3
-; GFX9-NEXT: v_mov_b32_e32 v0, s4
-; GFX9-NEXT: v_mov_b32_e32 v1, s5
-; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s2, v2, v[0:1]
; GFX9-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v3, s3
+; GFX9-NEXT: v_pk_mov_b32 v[0:1], s[4:5], s[4:5] op_sel:[0,1]
+; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s2, v3, v[0:1]
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]
; GFX9-NEXT: s_endpgm
%ext0 = zext i32 %arg0 to i64
@@ -542,8 +543,8 @@ define amdgpu_kernel void @mad_i64_i32_uniform(i64 addrspace(1)* %out, i32 %arg0
ret void
}
-define i64 @mad_i64_i32_multiple(i32 %arg0, i32 %arg1, i64 %arg2, i64 %arg3) #0 {
-; CI-LABEL: mad_i64_i32_multiple:
+define i64 @mad_i64_i32_twice(i32 %arg0, i32 %arg1, i64 %arg2, i64 %arg3) #0 {
+; CI-LABEL: mad_i64_i32_twice:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT: v_mad_i64_i32 v[2:3], s[4:5], v0, v1, v[2:3]
@@ -552,7 +553,7 @@ define i64 @mad_i64_i32_multiple(i32 %arg0, i32 %arg1, i64 %arg2, i64 %arg3) #0
; CI-NEXT: v_xor_b32_e32 v0, v2, v0
; CI-NEXT: s_setpc_b64 s[30:31]
;
-; SI-LABEL: mad_i64_i32_multiple:
+; SI-LABEL: mad_i64_i32_twice:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: v_mul_lo_u32 v6, v0, v1
@@ -565,7 +566,7 @@ define i64 @mad_i64_i32_multiple(i32 %arg0, i32 %arg1, i64 %arg2, i64 %arg3) #0
; SI-NEXT: v_xor_b32_e32 v0, v2, v3
; SI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-LABEL: mad_i64_i32_multiple:
+; GFX9-LABEL: mad_i64_i32_twice:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mad_i64_i32 v[2:3], s[4:5], v0, v1, v[2:3]
@@ -582,5 +583,94 @@ define i64 @mad_i64_i32_multiple(i32 %arg0, i32 %arg1, i64 %arg2, i64 %arg3) #0
ret i64 %out
}
+define i64 @mad_i64_i32_thrice(i32 %arg0, i32 %arg1, i64 %arg2, i64 %arg3, i64 %arg4) #0 {
+; CI-LABEL: mad_i64_i32_thrice:
+; CI: ; %bb.0:
+; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CI-NEXT: v_mad_i64_i32 v[2:3], s[4:5], v0, v1, v[2:3]
+; CI-NEXT: v_mad_i64_i32 v[4:5], s[4:5], v0, v1, v[4:5]
+; CI-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v0, v1, v[6:7]
+; CI-NEXT: v_xor_b32_e32 v3, v3, v5
+; CI-NEXT: v_xor_b32_e32 v2, v2, v4
+; CI-NEXT: v_xor_b32_e32 v1, v3, v1
+; CI-NEXT: v_xor_b32_e32 v0, v2, v0
+; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: mad_i64_i32_thrice:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_mul_lo_u32 v8, v0, v1
+; SI-NEXT: v_mul_hi_i32 v0, v0, v1
+; SI-NEXT: v_add_i32_e32 v1, vcc, v8, v2
+; SI-NEXT: v_addc_u32_e32 v2, vcc, v0, v3, vcc
+; SI-NEXT: v_add_i32_e32 v3, vcc, v8, v4
+; SI-NEXT: v_addc_u32_e32 v4, vcc, v0, v5, vcc
+; SI-NEXT: v_add_i32_e32 v5, vcc, v8, v6
+; SI-NEXT: v_addc_u32_e32 v0, vcc, v0, v7, vcc
+; SI-NEXT: v_xor_b32_e32 v2, v2, v4
+; SI-NEXT: v_xor_b32_e32 v3, v1, v3
+; SI-NEXT: v_xor_b32_e32 v1, v2, v0
+; SI-NEXT: v_xor_b32_e32 v0, v3, v5
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: mad_i64_i32_thrice:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mad_i64_i32 v[2:3], s[4:5], v0, v1, v[2:3]
+; GFX9-NEXT: v_mad_i64_i32 v[4:5], s[4:5], v0, v1, v[4:5]
+; GFX9-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v0, v1, v[6:7]
+; GFX9-NEXT: v_xor_b32_e32 v3, v3, v5
+; GFX9-NEXT: v_xor_b32_e32 v2, v2, v4
+; GFX9-NEXT: v_xor_b32_e32 v1, v3, v1
+; GFX9-NEXT: v_xor_b32_e32 v0, v2, v0
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+ %sext0 = sext i32 %arg0 to i64
+ %sext1 = sext i32 %arg1 to i64
+ %mul = mul i64 %sext0, %sext1
+ %mad1 = add i64 %mul, %arg2
+ %mad2 = add i64 %mul, %arg3
+ %mad3 = add i64 %mul, %arg4
+ %out.p = xor i64 %mad1, %mad2
+ %out = xor i64 %out.p, %mad3
+ ret i64 %out
+}
+
+define i64 @mad_i64_i32_secondary_use(i32 %arg0, i32 %arg1, i64 %arg2) #0 {
+; CI-LABEL: mad_i64_i32_secondary_use:
+; CI: ; %bb.0:
+; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CI-NEXT: v_mad_i64_i32 v[4:5], s[4:5], v0, v1, 0
+; CI-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v0, v1, v[2:3]
+; CI-NEXT: v_xor_b32_e32 v1, v1, v5
+; CI-NEXT: v_xor_b32_e32 v0, v0, v4
+; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-LABEL: mad_i64_i32_secondary_use:
+; SI: ; %bb.0:
+; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-NEXT: v_mul_lo_u32 v4, v0, v1
+; SI-NEXT: v_mul_hi_i32 v0, v0, v1
+; SI-NEXT: v_add_i32_e32 v2, vcc, v4, v2
+; SI-NEXT: v_addc_u32_e32 v1, vcc, v0, v3, vcc
+; SI-NEXT: v_xor_b32_e32 v1, v1, v0
+; SI-NEXT: v_xor_b32_e32 v0, v2, v4
+; SI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: mad_i64_i32_secondary_use:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mad_i64_i32 v[4:5], s[4:5], v0, v1, 0
+; GFX9-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v0, v1, v[2:3]
+; GFX9-NEXT: v_xor_b32_e32 v1, v1, v5
+; GFX9-NEXT: v_xor_b32_e32 v0, v0, v4
+; GFX9-NEXT: s_setpc_b64 s[30:31]
+ %sext0 = sext i32 %arg0 to i64
+ %sext1 = sext i32 %arg1 to i64
+ %mul = mul i64 %sext0, %sext1
+ %mad = add i64 %mul, %arg2
+ %out = xor i64 %mad, %mul
+ ret i64 %out
+}
+
attributes #0 = { nounwind }
attributes #1 = { nounwind readnone speculatable }
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