[PATCH] D123970: [RISCV] Add isCommutable to ADD/ADDW/MUL/AND/OR/XOR/MIN/MAX/CLMUL

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 423740.
craig.topper added a comment.

Add MachineCSE test for ADD and ADDW. I can exhaustively test the other instructions if anyone thinks that's important.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123970/new/

https://reviews.llvm.org/D123970

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoM.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/test/CodeGen/RISCV/machine-cse.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D123970.423740.patch
Type: text/x-patch
Size: 9576 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220419/8e93ae53/attachment.bin>