[PATCH] D124034: llvm-reduce: Fix mangling types of generic registers

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: markus, reames, qcolombet, MatzeB, aeubanks.
Herald added a project: All.
arsenm requested review of this revision.
Herald added a subscriber: wdng.
Herald added a project: LLVM.

https://reviews.llvm.org/D124034

Files:
  llvm/test/tools/llvm-reduce/mir/generic-vreg.mir
  llvm/test/tools/llvm-reduce/mir/preserve-mem-operands.mir
  llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp


Index: llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp
===================================================================
--- llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp
+++ llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp
@@ -23,7 +23,7 @@
 
 static Register getPrevDefOfRCInMBB(MachineBasicBlock &MBB,
                                     MachineBasicBlock::reverse_iterator &RI,
-                                    const RegClassOrRegBank &RC,
+                                    const RegClassOrRegBank &RC, LLT Ty,
                                     SetVector<MachineInstr *> &ExcludeMIs) {
   auto MRI = &MBB.getParent()->getRegInfo();
   for (MachineBasicBlock::reverse_instr_iterator E = MBB.instr_rend(); RI != E;
@@ -37,7 +37,7 @@
       if (Register::isPhysicalRegister(Reg))
         continue;
 
-      if (MRI->getRegClassOrRegBank(Reg) == RC &&
+      if (MRI->getRegClassOrRegBank(Reg) == RC && MRI->getType(Reg) == Ty &&
           !ExcludeMIs.count(MO.getParent()))
         return Reg;
     }
@@ -81,6 +81,8 @@
       auto UE = MRI->use_end();
 
       const auto &RegRC = MRI->getRegClassOrRegBank(Reg);
+      LLT RegTy = MRI->getType(Reg);
+
       Register NewReg = 0;
       // If this is not a physical register and there are some uses.
       if (UI != UE) {
@@ -88,7 +90,7 @@
         MachineBasicBlock *BB = MI->getParent();
         ++RI;
         while (NewReg == 0 && BB) {
-          NewReg = getPrevDefOfRCInMBB(*BB, RI, RegRC, ToDelete);
+          NewReg = getPrevDefOfRCInMBB(*BB, RI, RegRC, RegTy, ToDelete);
           // Prepare for idom(BB).
           if (auto *IDM = MDT.getNode(BB)->getIDom()) {
             BB = IDM->getBlock();
Index: llvm/test/tools/llvm-reduce/mir/preserve-mem-operands.mir
===================================================================
--- llvm/test/tools/llvm-reduce/mir/preserve-mem-operands.mir
+++ llvm/test/tools/llvm-reduce/mir/preserve-mem-operands.mir
@@ -21,14 +21,13 @@
 # RESULT: %{{[0-9]+}}:_(<2 x s32>) = G_LOAD %{{[0-9]+}}(p1) :: (load (<2 x s32>) from %ir.argptr1, addrspace 3)
 # RESULT: %{{[0-9]+}}:_(<2 x s32>) = G_LOAD %{{[0-9]+}}(p1) :: (load (<2 x s32>) from %ir.argptr1 + 8, addrspace 3)
 # RESULT: %{{[0-9]+}}:_(<2 x s32>) = G_LOAD %{{[0-9]+}}(p1) :: (load (<2 x s32>) from %ir.argptr1 + 12, align 4, basealign 8, addrspace 3)
-# RESULT: %{{[0-9]+}}:_(p3) = G_IMPLICIT_DEF
 # RESULT: G_STORE %{{[0-9]+}}(<2 x s32>), %{{[0-9]+}}(p3) :: (store (<2 x s32>) into %fixed-stack.0, addrspace 5)
 # RESULT: G_STORE %{{[0-9]+}}(<2 x s32>), %{{[0-9]+}}(p3) :: (store (<2 x s32>) into %stack.0, addrspace 5)
 # RESULT: G_STORE %{{[0-9]+}}(p3), %{{[0-9]+}}(p3) :: (store (p3), addrspace 5)
-# RESULT: %{{[0-9]+}}:_(s32) = G_LOAD %{{[0-9]+}}(p3) :: (load (s32) from call-entry @foo, addrspace 4)
+# RESULT: %{{[0-9]+}}:_(s32) = G_LOAD %{{[0-9]+}}(p0) :: (load (s32) from call-entry @foo, addrspace 4)
 # RESULT: %{{[0-9]+}}:_(s32) = G_LOAD %{{[0-9]+}}(p1) :: (load (s32) from constant-pool, addrspace 1)
-# RESULT: %{{[0-9]+}}:_(p1) = G_LOAD %{{[0-9]+}}(p3) :: (load (p1) from got, addrspace 4)
-# RESULT: %{{[0-9]+}}:_(p1) = G_LOAD %{{[0-9]+}}(p3) :: (load (p1) from jump-table, addrspace 4)
+# RESULT: %{{[0-9]+}}:_(p1) = G_LOAD %{{[0-9]+}}(p0) :: (load (p1) from got, addrspace 4)
+# RESULT: %{{[0-9]+}}:_(p1) = G_LOAD %{{[0-9]+}}(p0) :: (load (p1) from jump-table, addrspace 4)
 # RESULT: G_STORE %{{[0-9]+}}(<3 x s32>), %{{[0-9]+}}(p5) :: (store (<3 x s32>) into stack, align 8, addrspace 5)
 # RESULT: G_STORE %{{[0-9]+}}(<3 x s32>), %{{[0-9]+}}(p5) :: (store (<3 x s32>) into stack + 12, align 4, basealign 8, addrspace 5)
 --- |
Index: llvm/test/tools/llvm-reduce/mir/generic-vreg.mir
===================================================================
--- llvm/test/tools/llvm-reduce/mir/generic-vreg.mir
+++ llvm/test/tools/llvm-reduce/mir/generic-vreg.mir
@@ -12,13 +12,13 @@
 # CHECK-INTERESTINGNESS: G_IMPLICIT_DEF
 # CHECK-INTERESTINGNESS: G_STORE
 
-# RESULT: %v0:vgpr(s32) = COPY $vgpr0, implicit-def %9(p1), implicit-def %10(s64), implicit-def %11(s64)
-# RESULT-NEXT: %arst:_(<2 x s32>) = G_IMPLICIT_DEF
-# RESULT-NEXT: %aoeu:_(s64) = G_BITCAST %arst(<2 x s32>)
+# RESULT: %v0:vgpr(s32) = COPY $vgpr0, implicit-def %9(<2 x s16>), implicit-def %10(s64), implicit-def %11(s64), implicit-def %12(<2 x s32>)
+# RESULT-NEXT: %unused_load_ptr:sgpr(p1) = G_IMPLICIT_DEF
+# RESULT-NEXT: %aoeu:_(s64) = G_BITCAST %12(<2 x s32>)
 # RESULT-NEXT: %add:_(s64) = G_ADD %aoeu, %aoeu
 # RESULT-NEXT: %ptr:_(p1) = G_IMPLICIT_DEF
 # RESULT-NEXT: G_STORE %v0(s32), %ptr(p1) :: (store (s32), addrspace 1)
-# RESULT-NEXT: S_ENDPGM 0, implicit %add(s64), implicit %v0(s32), implicit %11(s64)
+# RESULT-NEXT: S_ENDPGM 0, implicit %add(s64), implicit %9(<2 x s16>), implicit %11(s64)
 
 ---
 name:            f


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