[PATCH] D124014: [AArch64] Correct isLegalAddressingMode for ldp/stp
chenglin.bi via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 19 10:26:39 PDT 2022
bcl5980 added inline comments.
================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:13217
+ // ldp/stp don't support scale
+ if (Ty->isSized() && DL.getTypeSizeInBits(Ty) > 64)
+ return false;
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I'm not sure if we have better way to check here. Can someone help to find some other clean solution?
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D124014/new/
https://reviews.llvm.org/D124014
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