[PATCH] D118979: [AArch64] Set maximum VF with shouldMaximizeVectorBandwidth

[JinGu Kang via Phabricator via llvm-commits]

jaykang10 added a comment.

It looks the SVE target's data layout is missing 512-bit vector's alignment. The data layout does not mention the alignment of 512-bit vector so the alignment is same with its size. It is bigger than stack's alignment which is 128-bits and it causes stack re-alignment...

For the stage2 failure with llvm-tablegen, the `ContractNodes` function of tablegen has loop which is vectorized with VF 128 because it has i1 type... I did not expect vectorization with VF 128... It causes lots of spill codes... On PrologEpilogInserter, the default stack size is 3584 bytes and the SVE stack size is 4416 bytes... We need to avoid the VF 512... Anyway, the `ContractNodes` is called recursively and the stack re-alignment causes wrong stack overwriting...

After setting up the 512-bit vector type's alignment as 128-bit, the stage2 failure is gone.

It could be ok to disable the `shouldMaximizeVectorBandwidth` for SVE... because it could need cost model change not only vector type alignment... Let me discuss it with the team more...


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D118979