[PATCH] D124005: llvm-reduce: Preserve subregisters and other fields for top block def
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 19 07:46:26 PDT 2022
arsenm created this revision.
arsenm added reviewers: markus, aeubanks, MatzeB, qcolombet.
Herald added a project: All.
arsenm requested review of this revision.
Herald added a subscriber: wdng.
Herald added a project: LLVM.
https://reviews.llvm.org/D124005
Files:
llvm/test/tools/llvm-reduce/mir/subreg-def0.mir
llvm/test/tools/llvm-reduce/mir/subreg-def1.mir
llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp
Index: llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp
===================================================================
--- llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp
+++ llvm/tools/llvm-reduce/deltas/ReduceInstructionsMIR.cpp
@@ -101,10 +101,17 @@
// If no dominating definition was found then add an implicit one to the
// first instruction in the entry block.
+
+ // FIXME: This should really insert IMPLICIT_DEF or G_IMPLICIT_DEF. We
+ // need to refine the reduction quality metric from number of serialized
+ // bytes to continue progressing if we're going to introduce new
+ // instructions.
if (!NewReg && TopMI) {
NewReg = MRI->cloneVirtualRegister(Reg);
TopMI->addOperand(MachineOperand::CreateReg(
- NewReg, true /*IsDef*/, true /*IsImp*/, false /*IsKill*/));
+ NewReg, true /*IsDef*/, true /*IsImp*/, false /*IsKill*/,
+ MO.isDead(), MO.isUndef(), MO.isEarlyClobber(), MO.getSubReg(),
+ /*IsDebug*/ false, MO.isInternalRead()));
}
// Update all uses.
Index: llvm/test/tools/llvm-reduce/mir/subreg-def1.mir
===================================================================
--- /dev/null
+++ llvm/test/tools/llvm-reduce/mir/subreg-def1.mir
@@ -0,0 +1,24 @@
+# REQUIRES: amdgpu-registered-target
+# RUN: llvm-reduce -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
+# RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t
+
+# CHECK-INTERESTINGNESS: %{{[0-9]+}}.sub0:vreg_64 = V_ADD_U32_e32 %{{[0-9]+}}.sub1, %{{[0-9]+}}.sub0, implicit $exec
+# CHECK-INTERESTINGNESS: %{{[0-9]+}}.sub0:vreg_64 = V_ADD_U32_e32 4, %{{[0-9]+}}.sub0, implicit $exec
+
+# RESULT: S_WAITCNT 0, implicit-def undef %2.sub1
+# RESULT-NEXT: %{{[0-9]+}}.sub0:vreg_64 = V_ADD_U32_e32 %{{[0-9]+}}.sub1, %{{[0-9]+}}.sub0, implicit $exec
+# RESULT-NEXT: %{{[0-9]+}}.sub0:vreg_64 = V_ADD_U32_e32 4, %{{[0-9]+}}.sub0, implicit $exec
+# RESULT-NEXT: S_ENDPGM 0, implicit %{{[0-9]+}}, implicit %{{[0-9]+}}.sub0
+
+---
+name: f
+tracksRegLiveness: true
+body: |
+ bb.0:
+ S_WAITCNT 0
+ undef %0.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
+ %1.sub1:vreg_64 = V_ADD_U32_e32 2, %0.sub1, implicit $exec
+ %0.sub0:vreg_64 = V_ADD_U32_e32 %1.sub1, %0.sub0, implicit $exec
+ %1.sub0:vreg_64 = V_ADD_U32_e32 4, %0.sub0, implicit $exec
+ S_ENDPGM 0, implicit %1, implicit %0.sub0
+...
Index: llvm/test/tools/llvm-reduce/mir/subreg-def0.mir
===================================================================
--- /dev/null
+++ llvm/test/tools/llvm-reduce/mir/subreg-def0.mir
@@ -0,0 +1,21 @@
+# REQUIRES: amdgpu-registered-target
+# RUN: llvm-reduce -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
+# RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t
+
+# CHECK-INTERESTINGNESS: V_ADD_U32
+
+# RESULT: S_WAITCNT 0, implicit-def undef %2.sub1, implicit-def %3.sub0
+# RESULT-NEXT: %1:vgpr_32 = V_ADD_U32_e32 %2.sub0, %2.sub1, implicit $exec
+# RESULT-NEXT: S_ENDPGM 0, implicit %1
+
+---
+name: f
+tracksRegLiveness: true
+body: |
+ bb.0:
+ S_WAITCNT 0
+ undef %0.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
+ %0.sub0:vreg_64 = V_MOV_B32_e32 1, implicit $exec
+ %1:vgpr_32 = V_ADD_U32_e32 %0.sub0, %0.sub1, implicit $exec
+ S_ENDPGM 0, implicit %1
+...
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