[PATCH] D123846: [RS4GC] Prune inputs of BDV if they are BDV themselves

[Dmitry Makogon via Phabricator via llvm-commits]

dmakogon added a comment.

In D123846#3453716 <https://reviews.llvm.org/D123846#3453716>, @mkazantsev wrote:

> Will this patch handle the following example:
>
>   loop: 
>     %outer_phi = phi (%start, %inner_phi)
>     br inner_loop
>   
>   inner_loop:
>     %inner_phi = phi(%start, %outer_phi)
>     %inner.cond = <smth>
>     br %inner.cond, inner_loop, outer_backedge
>   
>   outer_backedge:
>     outer_cond = ...
>     br outer_cond, loop, exit
>   
>   exit:
>   ...
>
> Here both `inner_phi` and `outer_phi` are in fact equal to one another (and both equal to `start`), but still different values. Will it work? If no, is there a plan to make it work?

No, these PHIs won't be removed at this stage of RS4GC. 
However there won't be any cloning here. During states meet phase we will figure out that they both have the %start base. Merging two equal bases is not a conflict state.


Repository:
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https://reviews.llvm.org/D123846