[llvm] 0053794 - [RISCV] Add tests showing incorrect BUILD_VECTOR lowering

[Fraser Cormack via llvm-commits]

Author: Fraser Cormack
Date: 2022-04-19T07:00:48+01:00
New Revision: 00537946aa29928894ba140687de1b6f9494e44d

URL: https://github.com/llvm/llvm-project/commit/00537946aa29928894ba140687de1b6f9494e44d
DIFF: https://github.com/llvm/llvm-project/commit/00537946aa29928894ba140687de1b6f9494e44d.diff

LOG: [RISCV] Add tests showing incorrect BUILD_VECTOR lowering

These tests both use vector constants misidentified as VID sequences.
Because the initial run of elements has a zero step, the elements are
skipped until such a step can be identified. The bug is that the skipped
elements are never validated, even though the computed step is
incompatible across the entire sequence.

A fix will follow in a subseqeuent patch.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D123785

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
index 93b745ca140d2..176df35376a64 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
@@ -723,3 +723,24 @@ define <8 x i16> @splat_idx_v8i16(<8 x i16> %v, i64 %idx) {
   %splat = shufflevector <8 x i16> %ins, <8 x i16> poison, <8 x i32> zeroinitializer
   ret <8 x i16> %splat
 }
+
+; FIXME: This is not a vid sequence!
+define <4 x i8> @buildvec_not_vid_v4i8_1() {
+; CHECK-LABEL: buildvec_not_vid_v4i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, mu
+; CHECK-NEXT:    vid.v v8
+; CHECK-NEXT:    ret
+  ret <4 x i8> <i8 0, i8 0, i8 2, i8 3>
+}
+
+; FIXME: This is not a vid sequence!
+define <4 x i8> @buildvec_not_vid_v4i8_2() {
+; CHECK-LABEL: buildvec_not_vid_v4i8_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, mu
+; CHECK-NEXT:    vid.v v8
+; CHECK-NEXT:    vrsub.vi v8, v8, 3
+; CHECK-NEXT:    ret
+  ret <4 x i8> <i8 3, i8 3, i8 1, i8 0>
+}