[PATCH] D123264: [RISCV] Pre-RA expand pseudos pass
Luís Marques via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 18 16:26:25 PDT 2022
luismarques updated this revision to Diff 423484.
luismarques marked 2 inline comments as done.
luismarques edited the summary of this revision.
luismarques added a comment.
Don't mess with isPosition. Create named temp labels. Remove cruft.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D123264/new/
https://reviews.llvm.org/D123264
Files:
llvm/lib/CodeGen/MachineInstr.cpp
llvm/lib/Target/RISCV/RISCV.h
llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
llvm/test/CodeGen/RISCV/O3-pipeline.ll
llvm/test/CodeGen/RISCV/codemodel-lowering.ll
llvm/test/CodeGen/RISCV/elf-preemption.ll
llvm/test/CodeGen/RISCV/jumptable.ll
llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll
llvm/test/CodeGen/RISCV/mir-target-flags-medium.ll
llvm/test/CodeGen/RISCV/mir-target-flags-small.ll
llvm/test/CodeGen/RISCV/mir-target-flags.ll
llvm/test/CodeGen/RISCV/pic-models.ll
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