[PATCH] D116072: [X86] GLC: Break false dependency for dest register for several instructions.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon requested changes to this revision.
RKSimon added a comment.
This revision now requires changes to proceed.

A few minors to address



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Comment at: llvm/lib/Target/X86/X86.td:588
-                                    "Use alias analysis during codegen">;
-
 //===----------------------------------------------------------------------===//
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This change should be a separate patch


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Comment at: llvm/lib/Target/X86/X86Subtarget.h:265
+  bool HasMULLQFalseDeps = false;
+
   /// True if its preferable to combine to a single cross-lane shuffle
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Move this block above HasSBBDepBreaking so all the FalseDeps attributes are together


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Comment at: llvm/lib/Target/X86/X86Subtarget.h:702
+  bool hasGETMANTFalseDeps() const { return HasGETMANTFalseDeps; }
+  bool hasMULLQFalseDeps() const { return HasMULLQFalseDeps; }
   bool hasBMI() const { return HasBMI; }
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Don't put these here - move them below hasLZCNTFalseDeps() further down


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Comment at: llvm/test/CodeGen/X86/cmul-false-deps.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O3 -disable-peephole -verify-machineinstrs -mcpu=sapphirerapids -mtriple=x86_64-unknown-unknown < %s | FileCheck %s
+
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Do you need -O3?

Add a RUNs that use the +/- false-deps-cmul attribute to check that it works - same for all other test files,


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116072/new/

https://reviews.llvm.org/D116072