[llvm] 9cae511 - [InstCombine] Add additional test coverage for D123374

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2022-04-18T13:25:24+01:00
New Revision: 9cae511aa15af1491823b74ca84a3c88afe0cbab

URL: https://github.com/llvm/llvm-project/commit/9cae511aa15af1491823b74ca84a3c88afe0cbab
DIFF: https://github.com/llvm/llvm-project/commit/9cae511aa15af1491823b74ca84a3c88afe0cbab.diff

LOG: [InstCombine] Add additional test coverage for D123374

More basic test coverage for the fold: (A & 2^C1) + A => A & (2^C1 - 1) iff bit C1 in A is a sign bit

Added: 
    llvm/test/Transforms/InstCombine/add-mask.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/InstCombine/add-mask.ll b/llvm/test/Transforms/InstCombine/add-mask.ll
new file mode 100644
index 0000000000000..d0481f2720be7
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/add-mask.ll
@@ -0,0 +1,85 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -passes=instcombine -S | FileCheck %s
+
+;
+; (A & 2^C1) + A => A & (2^C1 - 1) iff bit C1 in A is a sign bit
+;
+
+define i32 @add_mask_sign_i32(i32 %x) {
+; CHECK-LABEL: @add_mask_sign_i32(
+; CHECK-NEXT:    [[A:%.*]] = ashr i32 [[X:%.*]], 31
+; CHECK-NEXT:    [[M:%.*]] = and i32 [[A]], 8
+; CHECK-NEXT:    [[R:%.*]] = add nsw i32 [[M]], [[A]]
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %a = ashr i32 %x, 31
+  %m = and i32 %a, 8
+  %r = add i32 %m, %a
+  ret i32 %r
+}
+
+define i32 @add_mask_sign_commute_i32(i32 %x) {
+; CHECK-LABEL: @add_mask_sign_commute_i32(
+; CHECK-NEXT:    [[A:%.*]] = ashr i32 [[X:%.*]], 31
+; CHECK-NEXT:    [[M:%.*]] = and i32 [[A]], 8
+; CHECK-NEXT:    [[R:%.*]] = add nsw i32 [[A]], [[M]]
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %a = ashr i32 %x, 31
+  %m = and i32 %a, 8
+  %r = add i32 %a, %m
+  ret i32 %r
+}
+
+define <2 x i32> @add_mask_sign_v2i32(<2 x i32> %x) {
+; CHECK-LABEL: @add_mask_sign_v2i32(
+; CHECK-NEXT:    [[A:%.*]] = ashr <2 x i32> [[X:%.*]], <i32 31, i32 31>
+; CHECK-NEXT:    [[M:%.*]] = and <2 x i32> [[A]], <i32 8, i32 8>
+; CHECK-NEXT:    [[R:%.*]] = add nsw <2 x i32> [[M]], [[A]]
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %a = ashr <2 x i32> %x, <i32 31, i32 31>
+  %m = and <2 x i32> %a, <i32 8, i32 8>
+  %r = add <2 x i32> %m, %a
+  ret <2 x i32> %r
+}
+
+define <2 x i32> @add_mask_sign_v2i32_nonuniform(<2 x i32> %x) {
+; CHECK-LABEL: @add_mask_sign_v2i32_nonuniform(
+; CHECK-NEXT:    [[A:%.*]] = ashr <2 x i32> [[X:%.*]], <i32 30, i32 31>
+; CHECK-NEXT:    [[M:%.*]] = and <2 x i32> [[A]], <i32 8, i32 16>
+; CHECK-NEXT:    [[R:%.*]] = add <2 x i32> [[M]], [[A]]
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %a = ashr <2 x i32> %x, <i32 30, i32 31>
+  %m = and <2 x i32> %a, <i32 8, i32 16>
+  %r = add <2 x i32> %m, %a
+  ret <2 x i32> %r
+}
+
+define i32 @add_mask_ashr28_i32(i32 %x) {
+; CHECK-LABEL: @add_mask_ashr28_i32(
+; CHECK-NEXT:    [[A:%.*]] = ashr i32 [[X:%.*]], 28
+; CHECK-NEXT:    [[M:%.*]] = and i32 [[A]], 8
+; CHECK-NEXT:    [[R:%.*]] = add nsw i32 [[M]], [[A]]
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %a = ashr i32 %x, 28
+  %m = and i32 %a, 8
+  %r = add i32 %m, %a
+  ret i32 %r
+}
+
+; negative case - insufficient sign bits
+define i32 @add_mask_ashr27_i32(i32 %x) {
+; CHECK-LABEL: @add_mask_ashr27_i32(
+; CHECK-NEXT:    [[A:%.*]] = ashr i32 [[X:%.*]], 27
+; CHECK-NEXT:    [[M:%.*]] = and i32 [[A]], 8
+; CHECK-NEXT:    [[R:%.*]] = add nsw i32 [[M]], [[A]]
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %a = ashr i32 %x, 27
+  %m = and i32 %a, 8
+  %r = add i32 %m, %a
+  ret i32 %r
+}