[PATCH] D123841: [RISCV] Add rvv codegen support for vp.fptrunc.

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:3284
+  case ISD::FP_ROUND:
+    if (!Op.getValueType().isVector())
+      return Op;
----------------
craig.topper wrote:
> This check wasn't in the original code. Why is it needed now?
There is a branch that will just return Op when Op is not a vector in the original code.

```
if (!VT.isVector() || VT.getVectorElementType() != MVT::f16 ||
        SrcVT.getVectorElementType() != MVT::f64) {
      // For scalable vectors, we only need to close the gap between
      // vXf64<->vXf16.
      if (!VT.isFixedLengthVector())
        return Op;

...

}
```
These two ifs contain the no vector type situation, I split it out because this new lowering function only focus the vector FP round.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D123841/new/

https://reviews.llvm.org/D123841