[llvm] a5b7ea0 - [llvm-objdump] Implemented PrintBranchImmAsAddress for MIPS
Pavel Kosov via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 15 14:48:48 PDT 2022
Author: Pavel Kosov
Date: 2022-04-15T23:48:38+02:00
New Revision: a5b7ea0783f700bff897358d7c248742296978a2
URL: https://github.com/llvm/llvm-project/commit/a5b7ea0783f700bff897358d7c248742296978a2
DIFF: https://github.com/llvm/llvm-project/commit/a5b7ea0783f700bff897358d7c248742296978a2.diff
LOG: [llvm-objdump] Implemented PrintBranchImmAsAddress for MIPS
Updated MipsInstPrinter to print absolute hex offsets for branch instructions.
It is necessary to make the llvm-objdump output close to the gnu objdump output.
This implementation is based on the implementation for RISC-V.
OS Laboratory. Huawei Russian Research Institute. Saint-Petersburg
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D123764
Added:
Modified:
lld/test/ELF/mips-jalr-non-functions.s
lld/test/ELF/mips-jalr.s
lld/test/ELF/mips-micro-plt.s
lld/test/ELF/mips-micro-relocs.s
lld/test/ELF/mips-micro-thunks.s
lld/test/ELF/mips-micror6-relocs.s
lld/test/ELF/mips-npic-call-pic-script.s
lld/test/ELF/mips-npic-call-pic.s
lld/test/ELF/mips-pc-relocs.s
lld/test/ELF/mips-plt-n32.s
lld/test/ELF/mips-plt-n64.s
lld/test/ELF/mips-plt-r6.s
llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp
llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h
llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
llvm/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/lib/Target/Mips/Mips.td
llvm/lib/Target/Mips/Mips32r6InstrInfo.td
llvm/lib/Target/Mips/MipsInstrInfo.td
llvm/test/CodeGen/Mips/micromips-b-range.ll
llvm/test/MC/Mips/expansion-j-sym-pic.s
llvm/test/MC/Mips/instr-analysis.s
llvm/test/MC/Mips/micromips-el-fixup-data.s
llvm/test/MC/Mips/micromips-jump-pc-region.s
llvm/test/MC/Mips/micromips-neg-offset.s
llvm/test/MC/Mips/mips-jump-pc-region.s
Removed:
################################################################################
diff --git a/lld/test/ELF/mips-jalr-non-functions.s b/lld/test/ELF/mips-jalr-non-functions.s
index 0b1cb75ca6228..2ac58151fecba 100644
--- a/lld/test/ELF/mips-jalr-non-functions.s
+++ b/lld/test/ELF/mips-jalr-non-functions.s
@@ -54,5 +54,5 @@ reg_obj:
# CHECK-NEXT: nop
# CHECK-NEXT: jr $25
# CHECK-NEXT: nop
-# CHECK-NEXT: b 8 <untyped>
+# CHECK-NEXT: b {{.*}} <untyped>
# CHECK-NEXT: nop
diff --git a/lld/test/ELF/mips-jalr.s b/lld/test/ELF/mips-jalr.s
index 87a64b258c197..7084a592a662b 100644
--- a/lld/test/ELF/mips-jalr.s
+++ b/lld/test/ELF/mips-jalr.s
@@ -16,19 +16,19 @@
# REL: R_MIPS_JALR {{.*}} far
# SO: jalr $25
-# SO: bal -24 <foo>
+# SO: bal {{.*}} <foo>
# SO: jalr $25
# SO: jr $25
-# SO: b -64 <foo>
+# SO: b {{.*}} <foo>
# SO: jr $25
-# EXE: bal -4 <foo>
-# EXE: bal -24 <foo>
+# EXE: bal {{.*}} <foo>
+# EXE: bal {{.*}} <foo>
# EXE: jalr $25
-# EXE: b -56 <foo>
-# EXE: b -64 <foo>
+# EXE: b {{.*}} <foo>
+# EXE: b {{.*}} <foo>
# EXE: jr $25
.text
diff --git a/lld/test/ELF/mips-micro-plt.s b/lld/test/ELF/mips-micro-plt.s
index bf6a9dcfc65df..056b346357bba 100644
--- a/lld/test/ELF/mips-micro-plt.s
+++ b/lld/test/ELF/mips-micro-plt.s
@@ -42,7 +42,7 @@
# ASM-NEXT: addi $8, $8, 801
#
# ASM: <foo>:
-# ASM-NEXT: 20210: jal 131872
+# ASM-NEXT: 20210: jal 0x20320
.text
.set micromips
diff --git a/lld/test/ELF/mips-micro-relocs.s b/lld/test/ELF/mips-micro-relocs.s
index 1a6853baf81fb..46c989b886e85 100644
--- a/lld/test/ELF/mips-micro-relocs.s
+++ b/lld/test/ELF/mips-micro-relocs.s
@@ -46,11 +46,11 @@
# ASM-NEXT: addiu $3, $3, 32495
# ASM-NEXT: lw $3, -32744($gp)
# ASM-NEXT: lw $3, -32744($3)
-# ASM-NEXT: beqz16 $6, -32
+# ASM-NEXT: beqz16 $6, 0x20100
# ASM-NEXT: sll $3, $fp, 0
-# ASM-NEXT: b16 -40
+# ASM-NEXT: b16 0x200fe
# ASM-NEXT: nop
-# ASM-NEXT: b -44
+# ASM-NEXT: b 0x20100
# ELF: Entry point address: 0x20111
diff --git a/lld/test/ELF/mips-micro-thunks.s b/lld/test/ELF/mips-micro-thunks.s
index 80d62931d6198..8019131ec69df 100644
--- a/lld/test/ELF/mips-micro-thunks.s
+++ b/lld/test/ELF/mips-micro-thunks.s
@@ -42,22 +42,22 @@
# RUN: | FileCheck --check-prefix=R6 %s
# R2: <__start>:
-# R2-NEXT: 20100: jal 131336 <__microLA25Thunk_foo>
+# R2-NEXT: 20100: jal {{.*}} <__microLA25Thunk_foo>
# R2-NEXT: nop
# R2: <__microLA25Thunk_foo>:
# R2-NEXT: 20108: lui $25, 2
-# R2-NEXT: j 131360 <foo>
+# R2-NEXT: j {{.*}} <foo>
# R2-NEXT: addiu $25, $25, 289
# R2-NEXT: nop
# R6: <__start>:
-# R6-NEXT: 20100: balc 0 <__start>
+# R6-NEXT: 20100: balc {{.*}} <__start>
# R6: <__microLA25Thunk_foo>:
# R6-NEXT: 20104: lui $25, 2
# R6-NEXT: addiu $25, $25, 273
-# R6-NEXT: bc 0 <__microLA25Thunk_foo+0x8>
+# R6-NEXT: bc {{.*}} <__microLA25Thunk_foo+0x8>
.text
.set micromips
diff --git a/lld/test/ELF/mips-micror6-relocs.s b/lld/test/ELF/mips-micror6-relocs.s
index 36fd3aa2b5679..3606e10b4e8b2 100644
--- a/lld/test/ELF/mips-micror6-relocs.s
+++ b/lld/test/ELF/mips-micror6-relocs.s
@@ -25,8 +25,8 @@
# CHECK: <__start>:
# CHECK-NEXT: 20110: lapc $2, -12
-# CHECK-NEXT: beqzc $3, -36
-# CHECK-NEXT: balc -24 <foo>
+# CHECK-NEXT: beqzc $3, 0x200f0
+# CHECK-NEXT: balc {{.*}} <foo>
.text
.set micromips
diff --git a/lld/test/ELF/mips-npic-call-pic-script.s b/lld/test/ELF/mips-npic-call-pic-script.s
index 041c62101f7ff..fef7208267ee9 100644
--- a/lld/test/ELF/mips-npic-call-pic-script.s
+++ b/lld/test/ELF/mips-npic-call-pic-script.s
@@ -17,13 +17,13 @@
# CHECK-EMPTY:
# CHECK-NEXT: <__LA25Thunk_foo1a>:
# CHECK-NEXT: 20000: lui $25, 2
-# CHECK-NEXT: 20004: j 131104 <foo1a>
+# CHECK-NEXT: 20004: j {{.*}} <foo1a>
# CHECK-NEXT: 20008: addiu $25, $25, 32
# CHECK-NEXT: 2000c: nop
# CHECK: <__LA25Thunk_foo1b>:
# CHECK-NEXT: 20010: lui $25, 2
-# CHECK-NEXT: 20014: j 131108 <foo1b>
+# CHECK-NEXT: 20014: j {{.*}} <foo1b>
# CHECK-NEXT: 20018: addiu $25, $25, 36
# CHECK-NEXT: 2001c: nop
@@ -35,7 +35,7 @@
# CHECK: <__LA25Thunk_foo2>:
# CHECK-NEXT: 20028: lui $25, 2
-# CHECK-NEXT: 2002c: j 131136 <foo2>
+# CHECK-NEXT: 2002c: j {{.*}} <foo2>
# CHECK-NEXT: 20030: addiu $25, $25, 64
# CHECK-NEXT: 20034: nop
@@ -43,22 +43,22 @@
# CHECK-NEXT: 20040: nop
# CHECK: <__start>:
-# CHECK-NEXT: 20150: jal 131072 <__LA25Thunk_foo1a>
+# CHECK-NEXT: 20150: jal {{.*}} <__LA25Thunk_foo1a>
# CHECK-NEXT: 20154: nop
-# CHECK-NEXT: 20158: jal 131112 <__LA25Thunk_foo2>
+# CHECK-NEXT: 20158: jal {{.*}} <__LA25Thunk_foo2>
# CHECK-NEXT: 2015c: nop
-# CHECK-NEXT: 20160: jal 131088 <__LA25Thunk_foo1b>
+# CHECK-NEXT: 20160: jal {{.*}} <__LA25Thunk_foo1b>
# CHECK-NEXT: 20164: nop
-# CHECK-NEXT: 20168: jal 131112 <__LA25Thunk_foo2>
+# CHECK-NEXT: 20168: jal {{.*}} <__LA25Thunk_foo2>
# CHECK-NEXT: 2016c: nop
-# CHECK-NEXT: 20170: jal 131456 <__LA25Thunk_fpic>
+# CHECK-NEXT: 20170: jal {{.*}} <__LA25Thunk_fpic>
# CHECK-NEXT: 20174: nop
-# CHECK-NEXT: 20178: jal 131488 <fnpic>
+# CHECK-NEXT: 20178: jal {{.*}} <fnpic>
# CHECK-NEXT: 2017c: nop
# CHECK: <__LA25Thunk_fpic>:
# CHECK-NEXT: 20180: lui $25, 2
-# CHECK-NEXT: 20184: j 131472 <fpic>
+# CHECK-NEXT: 20184: j {{.*}} <fpic>
# CHECK-NEXT: 20188: addiu $25, $25, 400
# CHECK-NEXT: 2018c: nop
@@ -87,22 +87,22 @@ __start:
# ORPH1: Disassembly of section .text:
# ORPH1-EMPTY:
# ORPH1-NEXT: <__start>:
-# ORPH1-NEXT: 20000: jal 131168 <__LA25Thunk_foo1a>
+# ORPH1-NEXT: 20000: jal {{.*}} <__LA25Thunk_foo1a>
# ORPH1-NEXT: 20004: nop
-# ORPH1-NEXT: 20008: jal 131216 <__LA25Thunk_foo2>
+# ORPH1-NEXT: 20008: jal {{.*}} <__LA25Thunk_foo2>
# ORPH1-NEXT: 2000c: nop
-# ORPH1-NEXT: 20010: jal 131184 <__LA25Thunk_foo1b>
+# ORPH1-NEXT: 20010: jal {{.*}} <__LA25Thunk_foo1b>
# ORPH1-NEXT: 20014: nop
-# ORPH1-NEXT: 20018: jal 131216 <__LA25Thunk_foo2>
+# ORPH1-NEXT: 20018: jal {{.*}} <__LA25Thunk_foo2>
# ORPH1-NEXT: 2001c: nop
-# ORPH1-NEXT: 20020: jal 131120 <__LA25Thunk_fpic>
+# ORPH1-NEXT: 20020: jal {{.*}} <__LA25Thunk_fpic>
# ORPH1-NEXT: 20024: nop
-# ORPH1-NEXT: 20028: jal 131152 <fnpic>
+# ORPH1-NEXT: 20028: jal {{.*}} <fnpic>
# ORPH1-NEXT: 2002c: nop
# ORPH1: <__LA25Thunk_fpic>:
# ORPH1-NEXT: 20030: lui $25, 2
-# ORPH1-NEXT: 20034: j 131136 <fpic>
+# ORPH1-NEXT: 20034: j {{.*}} <fpic>
# ORPH1-NEXT: 20038: addiu $25, $25, 64
# ORPH1-NEXT: 2003c: nop
@@ -114,13 +114,13 @@ __start:
# ORPH1: <__LA25Thunk_foo1a>:
# ORPH1-NEXT: 20060: lui $25, 2
-# ORPH1-NEXT: j 131200 <foo1a>
+# ORPH1-NEXT: j {{.*}} <foo1a>
# ORPH1-NEXT: addiu $25, $25, 128
# ORPH1-NEXT: nop
# ORPH1: <__LA25Thunk_foo1b>:
# ORPH1-NEXT: 20070: lui $25, 2
-# ORPH1-NEXT: j 131204 <foo1b>
+# ORPH1-NEXT: j {{.*}} <foo1b>
# ORPH1-NEXT: addiu $25, $25, 132
# ORPH1-NEXT: nop
@@ -132,7 +132,7 @@ __start:
# ORPH1: <__LA25Thunk_foo2>:
# ORPH1-NEXT: 20090: lui $25, 2
-# ORPH1-NEXT: j 131232 <foo2>
+# ORPH1-NEXT: j {{.*}} <foo2>
# ORPH1-NEXT: addiu $25, $25, 160
# ORPH1-NEXT: nop
@@ -148,22 +148,22 @@ __start:
# ORPH2: Disassembly of section .out:
# ORPH2-EMPTY:
# ORPH2-NEXT: <__start>:
-# ORPH2-NEXT: 20000: jal 131168 <__LA25Thunk_foo1a>
+# ORPH2-NEXT: 20000: jal {{.*}} <__LA25Thunk_foo1a>
# ORPH2-NEXT: 20004: nop
-# ORPH2-NEXT: 20008: jal 131208 <__LA25Thunk_foo2>
+# ORPH2-NEXT: 20008: jal {{.*}} <__LA25Thunk_foo2>
# ORPH2-NEXT: 2000c: nop
-# ORPH2-NEXT: 20010: jal 131184 <__LA25Thunk_foo1b>
+# ORPH2-NEXT: 20010: jal {{.*}} <__LA25Thunk_foo1b>
# ORPH2-NEXT: 20014: nop
-# ORPH2-NEXT: 20018: jal 131208 <__LA25Thunk_foo2>
+# ORPH2-NEXT: 20018: jal {{.*}} <__LA25Thunk_foo2>
# ORPH2-NEXT: 2001c: nop
-# ORPH2-NEXT: 20020: jal 131120 <__LA25Thunk_fpic>
+# ORPH2-NEXT: 20020: jal {{.*}} <__LA25Thunk_fpic>
# ORPH2-NEXT: 20024: nop
-# ORPH2-NEXT: 20028: jal 131152 <fnpic>
+# ORPH2-NEXT: 20028: jal {{.*}} <fnpic>
# ORPH2-NEXT: 2002c: nop
# ORPH2: <__LA25Thunk_fpic>:
# ORPH2-NEXT: 20030: lui $25, 2
-# ORPH2-NEXT: 20034: j 131136 <fpic>
+# ORPH2-NEXT: 20034: j {{.*}} <fpic>
# ORPH2-NEXT: 20038: addiu $25, $25, 64
# ORPH2-NEXT: 2003c: nop
@@ -178,13 +178,13 @@ __start:
# ORPH2-NEXT: <__LA25Thunk_foo1a>:
# ORPH2-NEXT: 20060: lui $25, 2
-# ORPH2-NEXT: 20064: j 131200 <foo1a>
+# ORPH2-NEXT: 20064: j {{.*}} <foo1a>
# ORPH2-NEXT: 20068: addiu $25, $25, 128
# ORPH2-NEXT: 2006c: nop
# ORPH2: <__LA25Thunk_foo1b>:
# ORPH2-NEXT: 20070: lui $25, 2
-# ORPH2-NEXT: 20074: j 131204 <foo1b>
+# ORPH2-NEXT: 20074: j {{.*}} <foo1b>
# ORPH2-NEXT: 20078: addiu $25, $25, 132
# ORPH2-NEXT: 2007c: nop
@@ -196,7 +196,7 @@ __start:
# ORPH2: <__LA25Thunk_foo2>:
# ORPH2-NEXT: 20088: lui $25, 2
-# ORPH2-NEXT: 2008c: j 131232 <foo2>
+# ORPH2-NEXT: 2008c: j {{.*}} <foo2>
# ORPH2-NEXT: 20090: addiu $25, $25, 160
# ORPH2-NEXT: 20094: nop
diff --git a/lld/test/ELF/mips-npic-call-pic.s b/lld/test/ELF/mips-npic-call-pic.s
index 364476e7fabcf..9c2143e694d44 100644
--- a/lld/test/ELF/mips-npic-call-pic.s
+++ b/lld/test/ELF/mips-npic-call-pic.s
@@ -37,23 +37,23 @@
# CHECK: Disassembly of section .text:
# CHECK-EMPTY:
# CHECK-NEXT: <__start>:
-# CHECK-NEXT: 20100: jal 131412 <__LA25Thunk_foo1a>
+# CHECK-NEXT: 20100: jal {{.*}} <__LA25Thunk_foo1a>
# CHECK-NEXT: nop
-# CHECK-NEXT: jal 131464 <__LA25Thunk_foo2>
+# CHECK-NEXT: jal {{.*}} <__LA25Thunk_foo2>
# CHECK-NEXT: nop
-# CHECK-NEXT: jal 131428 <__LA25Thunk_foo1b>
+# CHECK-NEXT: jal {{.*}} <__LA25Thunk_foo1b>
# CHECK-NEXT: nop
-# CHECK-NEXT: jal 131464 <__LA25Thunk_foo2>
+# CHECK-NEXT: jal {{.*}} <__LA25Thunk_foo2>
# CHECK-NEXT: nop
-# CHECK-NEXT: jal 131376 <__LA25Thunk_fpic>
+# CHECK-NEXT: jal {{.*}} <__LA25Thunk_fpic>
# CHECK-NEXT: nop
-# CHECK-NEXT: jal 131408 <fnpic>
+# CHECK-NEXT: jal {{.*}} <fnpic>
# CHECK-NEXT: nop
# CHECK: <__LA25Thunk_fpic>:
# R2: 20130: lui $25, 2
# R6: 20130: aui $25, $zero, 2
-# CHECK-NEXT: j 131392 <fpic>
+# CHECK-NEXT: j {{.*}} <fpic>
# CHECK-NEXT: addiu $25, $25, 320
# CHECK-NEXT: nop
@@ -66,14 +66,14 @@
# CHECK: <__LA25Thunk_foo1a>:
# R2: 20154: lui $25, 2
# R6: 20154: aui $25, $zero, 2
-# CHECK: j 131456 <foo1a>
+# CHECK: j {{.*}} <foo1a>
# CHECK-NEXT: addiu $25, $25, 384
# CHECK-NEXT: nop
# CHECK: <__LA25Thunk_foo1b>:
# R2: 20164: lui $25, 2
# R6: aui $25, $zero, 2
-# CHECK-NEXT: j 131460 <foo1b>
+# CHECK-NEXT: j {{.*}} <foo1b>
# CHECK-NEXT: addiu $25, $25, 388
# CHECK-NEXT: nop
@@ -86,7 +86,7 @@
# CHECK: <__LA25Thunk_foo2>:
# R2: 20188: lui $25, 2
# R6: aui $25, $zero, 2
-# CHECK-NEXT: j 131488 <foo2>
+# CHECK-NEXT: j {{.*}} <foo2>
# CHECK-NEXT: addiu $25, $25, 416
# CHECK-NEXT: nop
diff --git a/lld/test/ELF/mips-pc-relocs.s b/lld/test/ELF/mips-pc-relocs.s
index 72dcee6f74584..1c2f609a02454 100644
--- a/lld/test/ELF/mips-pc-relocs.s
+++ b/lld/test/ELF/mips-pc-relocs.s
@@ -38,11 +38,11 @@ __start:
# CHECK-NEXT: <__start>:
# CHECK-NEXT: 20000: lwpc $6, 32
# ^-- (0x20020-0x20000)>>2
-# CHECK-NEXT: 20004: beqc $5, $6, 28
+# CHECK-NEXT: 20004: beqc $5, $6, 0x20020
# ^-- (0x20020-4-0x20004)>>2
-# CHECK-NEXT: 20008: beqzc $9, 24
+# CHECK-NEXT: 20008: beqzc $9, 0x20020
# ^-- (0x20020-4-0x20008)>>2
-# CHECK-NEXT: 2000c: bc 20
+# CHECK-NEXT: 2000c: bc 0x20020
# ^-- (0x20020-4-0x2000c)>>2
# CHECK-NEXT: 20010: aluipc $2, 0
# ^-- %hi(0x20020-0x20010)
diff --git a/lld/test/ELF/mips-plt-n32.s b/lld/test/ELF/mips-plt-n32.s
index 42ff8fd930d9c..fead6eac4209a 100644
--- a/lld/test/ELF/mips-plt-n32.s
+++ b/lld/test/ELF/mips-plt-n32.s
@@ -23,7 +23,7 @@
# CHECK: Disassembly of section .text:
# CHECK-EMPTY:
# CHECK-NEXT: <__start>:
-# CHECK-NEXT: 20000: jal 131120
+# CHECK-NEXT: 20000: jal 0x20030
# ^-- 0x20030 gotplt[foo0]
# CHECK-NEXT: 20004: nop
#
diff --git a/lld/test/ELF/mips-plt-n64.s b/lld/test/ELF/mips-plt-n64.s
index 4b49799c54c28..144f47acab39e 100644
--- a/lld/test/ELF/mips-plt-n64.s
+++ b/lld/test/ELF/mips-plt-n64.s
@@ -21,7 +21,7 @@
# CHECK: Disassembly of section .text:
# CHECK-EMPTY:
# CHECK-NEXT: <__start>:
-# CHECK-NEXT: 20000: jal 131120
+# CHECK-NEXT: 20000: jal 0x20030
# CHECK-NEXT: 20004: nop
# CHECK-EMPTY:
# CHECK-NEXT: Disassembly of section .plt:
diff --git a/lld/test/ELF/mips-plt-r6.s b/lld/test/ELF/mips-plt-r6.s
index 8da41b2279f67..e3507b27ba4e9 100644
--- a/lld/test/ELF/mips-plt-r6.s
+++ b/lld/test/ELF/mips-plt-r6.s
@@ -20,7 +20,7 @@
# CHECK: Disassembly of section .text:
# CHECK-EMPTY:
# CHECK-NEXT: <__start>:
-# CHECK-NEXT: 20000: jal 131120
+# CHECK-NEXT: 20000: jal 0x20030
# ^-- 0x20030 gotplt[foo0]
# CHECK-NEXT: 20004: nop
#
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp
index 3700d6309e1a0..632192103d38f 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp
@@ -88,29 +88,30 @@ void MipsInstPrinter::printInst(const MCInst *MI, uint64_t Address,
break;
case Mips::Save16:
O << "\tsave\t";
- printSaveRestore(MI, O);
+ printSaveRestore(MI, STI, O);
O << " # 16 bit inst\n";
return;
case Mips::SaveX16:
O << "\tsave\t";
- printSaveRestore(MI, O);
+ printSaveRestore(MI, STI, O);
O << "\n";
return;
case Mips::Restore16:
O << "\trestore\t";
- printSaveRestore(MI, O);
+ printSaveRestore(MI, STI, O);
O << " # 16 bit inst\n";
return;
case Mips::RestoreX16:
O << "\trestore\t";
- printSaveRestore(MI, O);
+ printSaveRestore(MI, STI, O);
O << "\n";
return;
}
// Try to print any aliases first.
- if (!printAliasInstr(MI, Address, O) && !printAlias(*MI, O))
- printInstruction(MI, Address, O);
+ if (!printAliasInstr(MI, Address, STI, O) &&
+ !printAlias(*MI, Address, STI, O))
+ printInstruction(MI, Address, STI, O);
printAnnotation(O, Annot);
switch (MI->getOpcode()) {
@@ -123,7 +124,7 @@ void MipsInstPrinter::printInst(const MCInst *MI, uint64_t Address,
}
void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
- raw_ostream &O) {
+ const MCSubtargetInfo &STI, raw_ostream &O) {
const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isReg()) {
printRegName(O, Op.getReg());
@@ -139,8 +140,42 @@ void MipsInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
Op.getExpr()->print(O, &MAI, true);
}
+void MipsInstPrinter::printJumpOperand(const MCInst *MI, unsigned OpNo,
+ const MCSubtargetInfo &STI,
+ raw_ostream &O) {
+ const MCOperand &Op = MI->getOperand(OpNo);
+ if (!Op.isImm())
+ return printOperand(MI, OpNo, STI, O);
+
+ if (PrintBranchImmAsAddress)
+ O << formatHex(Op.getImm());
+ else
+ O << formatImm(Op.getImm());
+}
+
+void MipsInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address,
+ unsigned OpNo,
+ const MCSubtargetInfo &STI,
+ raw_ostream &O) {
+ const MCOperand &Op = MI->getOperand(OpNo);
+ if (!Op.isImm())
+ return printOperand(MI, OpNo, STI, O);
+
+ if (PrintBranchImmAsAddress) {
+ uint64_t Target = Address + Op.getImm();
+ if (STI.hasFeature(Mips::FeatureMips32))
+ Target &= 0xffffffff;
+ else if (STI.hasFeature(Mips::FeatureMips16))
+ Target &= 0xffff;
+ O << formatHex(Target);
+ } else {
+ O << formatImm(Op.getImm());
+ }
+}
+
template <unsigned Bits, unsigned Offset>
-void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) {
+void MipsInstPrinter::printUImm(const MCInst *MI, int opNum,
+ const MCSubtargetInfo &STI, raw_ostream &O) {
const MCOperand &MO = MI->getOperand(opNum);
if (MO.isImm()) {
uint64_t Imm = MO.getImm();
@@ -151,11 +186,12 @@ void MipsInstPrinter::printUImm(const MCInst *MI, int opNum, raw_ostream &O) {
return;
}
- printOperand(MI, opNum, O);
+ printOperand(MI, opNum, STI, O);
}
-void MipsInstPrinter::
-printMemOperand(const MCInst *MI, int opNum, raw_ostream &O) {
+void MipsInstPrinter::printMemOperand(const MCInst *MI, int opNum,
+ const MCSubtargetInfo &STI,
+ raw_ostream &O) {
// Load/Store memory operands -- imm($reg)
// If PIC target the target is loaded as the
// pattern lw $25,%call16($28)
@@ -175,24 +211,26 @@ printMemOperand(const MCInst *MI, int opNum, raw_ostream &O) {
break;
}
- printOperand(MI, opNum+1, O);
+ printOperand(MI, opNum + 1, STI, O);
O << "(";
- printOperand(MI, opNum, O);
+ printOperand(MI, opNum, STI, O);
O << ")";
}
-void MipsInstPrinter::
-printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O) {
+void MipsInstPrinter::printMemOperandEA(const MCInst *MI, int opNum,
+ const MCSubtargetInfo &STI,
+ raw_ostream &O) {
// when using stack locations for not load/store instructions
// print the same way as all normal 3 operand instructions.
- printOperand(MI, opNum, O);
+ printOperand(MI, opNum, STI, O);
O << ", ";
- printOperand(MI, opNum+1, O);
+ printOperand(MI, opNum + 1, STI, O);
}
-void MipsInstPrinter::
-printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) {
- const MCOperand& MO = MI->getOperand(opNum);
+void MipsInstPrinter::printFCCOperand(const MCInst *MI, int opNum,
+ const MCSubtargetInfo & /* STI */,
+ raw_ostream &O) {
+ const MCOperand &MO = MI->getOperand(opNum);
O << MipsFCCToString((Mips::CondCode)MO.getImm());
}
@@ -202,82 +240,116 @@ printSHFMask(const MCInst *MI, int opNum, raw_ostream &O) {
}
bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
- unsigned OpNo, raw_ostream &OS) {
+ uint64_t Address, unsigned OpNo,
+ const MCSubtargetInfo &STI, raw_ostream &OS,
+ bool IsBranch) {
OS << "\t" << Str << "\t";
- printOperand(&MI, OpNo, OS);
+ if (IsBranch)
+ printBranchOperand(&MI, Address, OpNo, STI, OS);
+ else
+ printOperand(&MI, OpNo, STI, OS);
return true;
}
bool MipsInstPrinter::printAlias(const char *Str, const MCInst &MI,
- unsigned OpNo0, unsigned OpNo1,
- raw_ostream &OS) {
- printAlias(Str, MI, OpNo0, OS);
+ uint64_t Address, unsigned OpNo0,
+ unsigned OpNo1, const MCSubtargetInfo &STI,
+ raw_ostream &OS, bool IsBranch) {
+ printAlias(Str, MI, Address, OpNo0, STI, OS, IsBranch);
OS << ", ";
- printOperand(&MI, OpNo1, OS);
+ if (IsBranch)
+ printBranchOperand(&MI, Address, OpNo1, STI, OS);
+ else
+ printOperand(&MI, OpNo1, STI, OS);
return true;
}
-bool MipsInstPrinter::printAlias(const MCInst &MI, raw_ostream &OS) {
+bool MipsInstPrinter::printAlias(const MCInst &MI, uint64_t Address,
+ const MCSubtargetInfo &STI, raw_ostream &OS) {
switch (MI.getOpcode()) {
case Mips::BEQ:
case Mips::BEQ_MM:
// beq $zero, $zero, $L2 => b $L2
// beq $r0, $zero, $L2 => beqz $r0, $L2
return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) &&
- printAlias("b", MI, 2, OS)) ||
- (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS));
+ printAlias("b", MI, Address, 2, STI, OS, true)) ||
+ (isReg<Mips::ZERO>(MI, 1) &&
+ printAlias("beqz", MI, Address, 0, 2, STI, OS, true));
case Mips::BEQ64:
// beq $r0, $zero, $L2 => beqz $r0, $L2
- return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS);
+ return isReg<Mips::ZERO_64>(MI, 1) &&
+ printAlias("beqz", MI, Address, 0, 2, STI, OS, true);
case Mips::BNE:
case Mips::BNE_MM:
// bne $r0, $zero, $L2 => bnez $r0, $L2
- return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
+ return isReg<Mips::ZERO>(MI, 1) &&
+ printAlias("bnez", MI, Address, 0, 2, STI, OS, true);
case Mips::BNE64:
// bne $r0, $zero, $L2 => bnez $r0, $L2
- return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
+ return isReg<Mips::ZERO_64>(MI, 1) &&
+ printAlias("bnez", MI, Address, 0, 2, STI, OS, true);
case Mips::BGEZAL:
// bgezal $zero, $L1 => bal $L1
- return isReg<Mips::ZERO>(MI, 0) && printAlias("bal", MI, 1, OS);
+ return isReg<Mips::ZERO>(MI, 0) &&
+ printAlias("bal", MI, Address, 1, STI, OS, true);
case Mips::BC1T:
// bc1t $fcc0, $L1 => bc1t $L1
- return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1t", MI, 1, OS);
+ return isReg<Mips::FCC0>(MI, 0) &&
+ printAlias("bc1t", MI, Address, 1, STI, OS, true);
case Mips::BC1F:
// bc1f $fcc0, $L1 => bc1f $L1
- return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1f", MI, 1, OS);
+ return isReg<Mips::FCC0>(MI, 0) &&
+ printAlias("bc1f", MI, Address, 1, STI, OS, true);
case Mips::JALR:
+ // jalr $zero, $r1 => jr $r1
// jalr $ra, $r1 => jalr $r1
- return isReg<Mips::RA>(MI, 0) && printAlias("jalr", MI, 1, OS);
+ return (isReg<Mips::ZERO>(MI, 0) &&
+ printAlias("jr", MI, Address, 1, STI, OS)) ||
+ (isReg<Mips::RA>(MI, 0) &&
+ printAlias("jalr", MI, Address, 1, STI, OS));
case Mips::JALR64:
+ // jalr $zero, $r1 => jr $r1
// jalr $ra, $r1 => jalr $r1
- return isReg<Mips::RA_64>(MI, 0) && printAlias("jalr", MI, 1, OS);
+ return (isReg<Mips::ZERO_64>(MI, 0) &&
+ printAlias("jr", MI, Address, 1, STI, OS)) ||
+ (isReg<Mips::RA_64>(MI, 0) &&
+ printAlias("jalr", MI, Address, 1, STI, OS));
case Mips::NOR:
case Mips::NOR_MM:
case Mips::NOR_MMR6:
// nor $r0, $r1, $zero => not $r0, $r1
- return isReg<Mips::ZERO>(MI, 2) && printAlias("not", MI, 0, 1, OS);
+ return isReg<Mips::ZERO>(MI, 2) &&
+ printAlias("not", MI, Address, 0, 1, STI, OS);
case Mips::NOR64:
// nor $r0, $r1, $zero => not $r0, $r1
- return isReg<Mips::ZERO_64>(MI, 2) && printAlias("not", MI, 0, 1, OS);
+ return isReg<Mips::ZERO_64>(MI, 2) &&
+ printAlias("not", MI, Address, 0, 1, STI, OS);
case Mips::OR:
+ case Mips::ADDu:
// or $r0, $r1, $zero => move $r0, $r1
- return isReg<Mips::ZERO>(MI, 2) && printAlias("move", MI, 0, 1, OS);
- default: return false;
+ // addu $r0, $r1, $zero => move $r0, $r1
+ return isReg<Mips::ZERO>(MI, 2) &&
+ printAlias("move", MI, Address, 0, 1, STI, OS);
+ default:
+ return false;
}
}
-void MipsInstPrinter::printSaveRestore(const MCInst *MI, raw_ostream &O) {
+void MipsInstPrinter::printSaveRestore(const MCInst *MI,
+ const MCSubtargetInfo &STI,
+ raw_ostream &O) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
if (i != 0) O << ", ";
if (MI->getOperand(i).isReg())
printRegName(O, MI->getOperand(i).getReg());
else
- printUImm<16>(MI, i, O);
+ printUImm<16>(MI, i, STI, O);
}
}
-void MipsInstPrinter::
-printRegisterList(const MCInst *MI, int opNum, raw_ostream &O) {
+void MipsInstPrinter::printRegisterList(const MCInst *MI, int opNum,
+ const MCSubtargetInfo & /* STI */,
+ raw_ostream &O) {
// - 2 because register List is always first operand of instruction and it is
// always followed by memory operand (base + offset).
for (int i = opNum, e = MI->getNumOperands() - 2; i != e; ++i) {
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h
index 68b13bf1fcc35..d91612b15a1aa 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h
@@ -80,38 +80,50 @@ class MipsInstPrinter : public MCInstPrinter {
// Autogenerated by tblgen.
std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
- void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
+ void printInstruction(const MCInst *MI, uint64_t Address,
+ const MCSubtargetInfo &STI, raw_ostream &O);
static const char *getRegisterName(unsigned RegNo);
void printRegName(raw_ostream &OS, unsigned RegNo) const override;
void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
const MCSubtargetInfo &STI, raw_ostream &O) override;
- bool printAliasInstr(const MCInst *MI, uint64_t Address, raw_ostream &OS);
+ bool printAliasInstr(const MCInst *MI, uint64_t Address,
+ const MCSubtargetInfo &STI, raw_ostream &OS);
void printCustomAliasOperand(const MCInst *MI, uint64_t Address,
unsigned OpIdx, unsigned PrintMethodIdx,
- raw_ostream &O);
+ const MCSubtargetInfo &STI, raw_ostream &O);
private:
- void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
- void printOperand(const MCInst *MI, uint64_t /*Address*/, unsigned OpNum,
- raw_ostream &O) {
- printOperand(MI, OpNum, O);
- }
+ void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
+ raw_ostream &O);
+ void printJumpOperand(const MCInst *MI, unsigned OpNo,
+ const MCSubtargetInfo &STI, raw_ostream &O);
+ void printBranchOperand(const MCInst *MI, uint64_t Address, unsigned OpNo,
+ const MCSubtargetInfo &STI, raw_ostream &O);
template <unsigned Bits, unsigned Offset = 0>
- void printUImm(const MCInst *MI, int opNum, raw_ostream &O);
- void printMemOperand(const MCInst *MI, int opNum, raw_ostream &O);
- void printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O);
- void printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O);
+ void printUImm(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
+ raw_ostream &O);
+ void printMemOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
+ raw_ostream &O);
+ void printMemOperandEA(const MCInst *MI, int opNum,
+ const MCSubtargetInfo &STI, raw_ostream &O);
+ void printFCCOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
+ raw_ostream &O);
void printSHFMask(const MCInst *MI, int opNum, raw_ostream &O);
- bool printAlias(const char *Str, const MCInst &MI, unsigned OpNo,
- raw_ostream &OS);
- bool printAlias(const char *Str, const MCInst &MI, unsigned OpNo0,
- unsigned OpNo1, raw_ostream &OS);
- bool printAlias(const MCInst &MI, raw_ostream &OS);
- void printSaveRestore(const MCInst *MI, raw_ostream &O);
- void printRegisterList(const MCInst *MI, int opNum, raw_ostream &O);
+ bool printAlias(const char *Str, const MCInst &MI, uint64_t Address,
+ unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &OS,
+ bool IsBranch = false);
+ bool printAlias(const char *Str, const MCInst &MI, uint64_t Address,
+ unsigned OpNo0, unsigned OpNo1, const MCSubtargetInfo &STI,
+ raw_ostream &OS, bool IsBranch = false);
+ bool printAlias(const MCInst &MI, uint64_t Address,
+ const MCSubtargetInfo &STI, raw_ostream &OS);
+ void printSaveRestore(const MCInst *MI, const MCSubtargetInfo &STI,
+ raw_ostream &O);
+ void printRegisterList(const MCInst *MI, int opNum,
+ const MCSubtargetInfo &STI, raw_ostream &O);
};
} // end namespace llvm
diff --git a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
index b1a05388884bb..26cc6ac4dd388 100644
--- a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
+++ b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
@@ -15,6 +15,7 @@ def brtarget21_mm : Operand<OtherVT> {
let OperandType = "OPERAND_PCREL";
let DecoderMethod = "DecodeBranchTarget21MM";
let ParserMatchClass = MipsJumpTargetAsmOperand;
+ let PrintMethod = "printBranchOperand";
}
def brtarget26_mm : Operand<OtherVT> {
@@ -22,6 +23,7 @@ def brtarget26_mm : Operand<OtherVT> {
let OperandType = "OPERAND_PCREL";
let DecoderMethod = "DecodeBranchTarget26MM";
let ParserMatchClass = MipsJumpTargetAsmOperand;
+ let PrintMethod = "printBranchOperand";
}
def brtargetr6 : Operand<OtherVT> {
@@ -29,6 +31,7 @@ def brtargetr6 : Operand<OtherVT> {
let OperandType = "OPERAND_PCREL";
let DecoderMethod = "DecodeBranchTargetMM";
let ParserMatchClass = MipsJumpTargetAsmOperand;
+ let PrintMethod = "printBranchOperand";
}
def brtarget_lsl2_mm : Operand<OtherVT> {
@@ -38,6 +41,7 @@ def brtarget_lsl2_mm : Operand<OtherVT> {
// set with DecodeDisambiguates
let DecoderMethod = "";
let ParserMatchClass = MipsJumpTargetAsmOperand;
+ let PrintMethod = "printBranchOperand";
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
index 5f6354e19ebc7..2b9d3a8c3588c 100644
--- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td
@@ -163,10 +163,12 @@ def mem_mm_4sp : Operand<i32> {
def jmptarget_mm : Operand<OtherVT> {
let EncoderMethod = "getJumpTargetOpValueMM";
+ let PrintMethod = "printJumpOperand";
}
def calltarget_mm : Operand<iPTR> {
let EncoderMethod = "getJumpTargetOpValueMM";
+ let PrintMethod = "printJumpOperand";
}
def brtarget7_mm : Operand<OtherVT> {
@@ -174,6 +176,7 @@ def brtarget7_mm : Operand<OtherVT> {
let OperandType = "OPERAND_PCREL";
let DecoderMethod = "DecodeBranchTarget7MM";
let ParserMatchClass = MipsJumpTargetAsmOperand;
+ let PrintMethod = "printBranchOperand";
}
def brtarget10_mm : Operand<OtherVT> {
@@ -181,6 +184,7 @@ def brtarget10_mm : Operand<OtherVT> {
let OperandType = "OPERAND_PCREL";
let DecoderMethod = "DecodeBranchTarget10MM";
let ParserMatchClass = MipsJumpTargetAsmOperand;
+ let PrintMethod = "printBranchOperand";
}
def brtarget_mm : Operand<OtherVT> {
@@ -188,6 +192,7 @@ def brtarget_mm : Operand<OtherVT> {
let OperandType = "OPERAND_PCREL";
let DecoderMethod = "DecodeBranchTargetMM";
let ParserMatchClass = MipsJumpTargetAsmOperand;
+ let PrintMethod = "printBranchOperand";
}
def simm23_lsl2 : Operand<i32> {
@@ -1320,6 +1325,7 @@ let EncodingPredicates = [InMicroMips] in {
II_DIVU, 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>, ISA_MICROMIPS;
+ def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>, ISA_MICROMIPS;
def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>, ISA_MICROMIPS;
def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>, ISA_MICROMIPS;
def : MipsInstAlias<"ei", (EI_MM ZERO), 1>, ISA_MICROMIPS;
diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td
index 406760dc678c8..398c38e678ba3 100644
--- a/llvm/lib/Target/Mips/Mips.td
+++ b/llvm/lib/Target/Mips/Mips.td
@@ -268,8 +268,13 @@ def MipsAsmParserVariant : AsmParserVariant {
string RegisterPrefix = "$";
}
+def MipsAsmWriter : AsmWriter {
+ int PassSubtarget = 1;
+}
+
def Mips : Target {
let InstructionSet = MipsInstrInfo;
+ let AssemblyWriters = [MipsAsmWriter];
let AssemblyParsers = [MipsAsmParser];
let AssemblyParserVariants = [MipsAsmParserVariant];
let AllowRegisterRenaming = 1;
diff --git a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
index 192d0013d89c8..0ae946160477e 100644
--- a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
@@ -39,6 +39,7 @@ def brtarget21 : Operand<OtherVT> {
let OperandType = "OPERAND_PCREL";
let DecoderMethod = "DecodeBranchTarget21";
let ParserMatchClass = MipsJumpTargetAsmOperand;
+ let PrintMethod = "printBranchOperand";
}
def brtarget26 : Operand<OtherVT> {
@@ -46,6 +47,7 @@ def brtarget26 : Operand<OtherVT> {
let OperandType = "OPERAND_PCREL";
let DecoderMethod = "DecodeBranchTarget26";
let ParserMatchClass = MipsJumpTargetAsmOperand;
+ let PrintMethod = "printBranchOperand";
}
def jmpoffset16 : Operand<OtherVT> {
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td
index 089fed9ec0bf4..973f40a21deeb 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.td
@@ -833,22 +833,26 @@ def MipsJumpTargetAsmOperand : AsmOperandClass {
def jmptarget : Operand<OtherVT> {
let EncoderMethod = "getJumpTargetOpValue";
let ParserMatchClass = MipsJumpTargetAsmOperand;
+ let PrintMethod = "printJumpOperand";
}
def brtarget : Operand<OtherVT> {
let EncoderMethod = "getBranchTargetOpValue";
let OperandType = "OPERAND_PCREL";
let DecoderMethod = "DecodeBranchTarget";
let ParserMatchClass = MipsJumpTargetAsmOperand;
+ let PrintMethod = "printBranchOperand";
}
def brtarget1SImm16 : Operand<OtherVT> {
let EncoderMethod = "getBranchTargetOpValue1SImm16";
let OperandType = "OPERAND_PCREL";
let DecoderMethod = "DecodeBranchTarget1SImm16";
let ParserMatchClass = MipsJumpTargetAsmOperand;
+ let PrintMethod = "printBranchOperand";
}
def calltarget : Operand<iPTR> {
let EncoderMethod = "getJumpTargetOpValue";
let ParserMatchClass = MipsJumpTargetAsmOperand;
+ let PrintMethod = "printJumpOperand";
}
def imm64: Operand<i64>;
diff --git a/llvm/test/CodeGen/Mips/micromips-b-range.ll b/llvm/test/CodeGen/Mips/micromips-b-range.ll
index 91de859957031..0cb30ef9bd598 100644
--- a/llvm/test/CodeGen/Mips/micromips-b-range.ll
+++ b/llvm/test/CodeGen/Mips/micromips-b-range.ll
@@ -7,56 +7,56 @@
; CHECK-NEXT: 8: 03 22 11 50 addu $2, $2, $25
; CHECK-NEXT: c: fc 42 00 00 lw $2, 0($2)
; CHECK-NEXT: 10: 69 20 lw16 $2, 0($2)
-; CHECK-NEXT: 12: 40 c2 00 14 bgtz $2, 44 <foo+0x3e>
+; CHECK-NEXT: 12: 40 c2 00 14 bgtz $2, 0x3e <foo+0x3e>
; CHECK-NEXT: 16: 00 00 00 00 nop
; CHECK-NEXT: 1a: 33 bd ff f8 addiu $sp, $sp, -8
; CHECK-NEXT: 1e: fb fd 00 00 sw $ra, 0($sp)
; CHECK-NEXT: 22: 41 a1 00 01 lui $1, 1
-; CHECK-NEXT: 26: 40 60 00 02 bal 8 <foo+0x2e>
+; CHECK-NEXT: 26: 40 60 00 02 bal 0x2e <foo+0x2e>
; CHECK-NEXT: 2a: 30 21 04 69 addiu $1, $1, 1129
; CHECK-NEXT: 2e: 00 3f 09 50 addu $1, $ra, $1
; CHECK-NEXT: 32: ff fd 00 00 lw $ra, 0($sp)
; CHECK-NEXT: 36: 00 01 0f 3c jr $1
; CHECK-NEXT: 3a: 33 bd 00 08 addiu $sp, $sp, 8
-; CHECK-NEXT: 3e: 94 00 00 02 b 8 <foo+0x46>
+; CHECK-NEXT: 3e: 94 00 00 02 b 0x46 <foo+0x46>
; CHECK-NEXT: 42: 00 00 00 00 nop
; CHECK-NEXT: 46: 30 20 4e 1f addiu $1, $zero, 19999
-; CHECK-NEXT: 4a: b4 22 00 14 bne $2, $1, 44 <foo+0x76>
+; CHECK-NEXT: 4a: b4 22 00 14 bne $2, $1, 0x76 <foo+0x76>
; CHECK-NEXT: 4e: 00 00 00 00 nop
; CHECK-NEXT: 52: 33 bd ff f8 addiu $sp, $sp, -8
; CHECK-NEXT: 56: fb fd 00 00 sw $ra, 0($sp)
; CHECK-NEXT: 5a: 41 a1 00 01 lui $1, 1
-; CHECK-NEXT: 5e: 40 60 00 02 bal 8 <foo+0x66>
+; CHECK-NEXT: 5e: 40 60 00 02 bal 0x66 <foo+0x66>
; CHECK-NEXT: 62: 30 21 04 5d addiu $1, $1, 1117
; CHECK-NEXT: 66: 00 3f 09 50 addu $1, $ra, $1
; CHECK-NEXT: 6a: ff fd 00 00 lw $ra, 0($sp)
; CHECK-NEXT: 6e: 00 01 0f 3c jr $1
; CHECK-NEXT: 72: 33 bd 00 08 addiu $sp, $sp, 8
; CHECK-NEXT: 76: 30 20 27 0f addiu $1, $zero, 9999
-; CHECK-NEXT: 7a: 94 22 00 14 beq $2, $1, 44 <foo+0xa6>
+; CHECK-NEXT: 7a: 94 22 00 14 beq $2, $1, 0xa6 <foo+0xa6>
; CHECK-NEXT: 7e: 00 00 00 00 nop
; CHECK-NEXT: 82: 33 bd ff f8 addiu $sp, $sp, -8
; CHECK-NEXT: 86: fb fd 00 00 sw $ra, 0($sp)
; CHECK-NEXT: 8a: 41 a1 00 01 lui $1, 1
-; CHECK-NEXT: 8e: 40 60 00 02 bal 8 <foo+0x96>
+; CHECK-NEXT: 8e: 40 60 00 02 bal 0x96 <foo+0x96>
; CHECK-NEXT: 92: 30 21 04 2d addiu $1, $1, 1069
; CHECK-NEXT: 96: 00 3f 09 50 addu $1, $ra, $1
; CHECK-NEXT: 9a: ff fd 00 00 lw $ra, 0($sp)
; CHECK-NEXT: 9e: 00 01 0f 3c jr $1
; CHECK-NEXT: a2: 33 bd 00 08 addiu $sp, $sp, 8
; CHECK: ...
-; CHECK-NEXT: 1046a: 94 00 00 02 b 8 <foo+0x10472>
+; CHECK-NEXT: 1046a: 94 00 00 02 b 0x10472 <foo+0x10472>
; CHECK-NEXT: 1046e: 00 00 00 00 nop
; CHECK-NEXT: 10472: 33 bd ff f8 addiu $sp, $sp, -8
; CHECK-NEXT: 10476: fb fd 00 00 sw $ra, 0($sp)
; CHECK-NEXT: 1047a: 41 a1 00 01 lui $1, 1
-; CHECK-NEXT: 1047e: 40 60 00 02 bal 8 <foo+0x10486>
+; CHECK-NEXT: 1047e: 40 60 00 02 bal 0x10486 <foo+0x10486>
; CHECK-NEXT: 10482: 30 21 04 01 addiu $1, $1, 1025
; CHECK-NEXT: 10486: 00 3f 09 50 addu $1, $ra, $1
; CHECK-NEXT: 1048a: ff fd 00 00 lw $ra, 0($sp)
; CHECK-NEXT: 1048e: 00 01 0f 3c jr $1
; CHECK-NEXT: 10492: 33 bd 00 08 addiu $sp, $sp, 8
-; CHECK-NEXT: 10496: 94 00 00 02 b 8 <foo+0x1049e>
+; CHECK-NEXT: 10496: 94 00 00 02 b 0x1049e <foo+0x1049e>
@x = external global i32, align 4
diff --git a/llvm/test/MC/Mips/expansion-j-sym-pic.s b/llvm/test/MC/Mips/expansion-j-sym-pic.s
index 5856f56502976..1cc393925b772 100644
--- a/llvm/test/MC/Mips/expansion-j-sym-pic.s
+++ b/llvm/test/MC/Mips/expansion-j-sym-pic.s
@@ -38,9 +38,9 @@ local_label:
# MICRO: b local_label # encoding: [0x94,0x00,A,A]
# MICRO: # fixup A - offset: 0, value: local_label, kind: fixup_MICROMIPS_PC16_S1
-# ELF-O32: 10 00 ff ff b 0
+# ELF-O32: 10 00 ff ff b 0x0 <local_label>
-# ELF-NXX: 10 00 ff ff b 0
+# ELF-NXX: 10 00 ff ff b 0x0 <local_label>
j weak_label
nop
@@ -51,10 +51,10 @@ local_label:
# MICRO: b weak_label # encoding: [0x94,0x00,A,A]
# MICRO: # fixup A - offset: 0, value: weak_label, kind: fixup_MICROMIPS_PC16_S1
-# ELF-O32: 10 00 ff ff b 0
+# ELF-O32: 10 00 ff ff b 0x8 <local_label+0x8>
# ELF-O32-NEXT: R_MIPS_PC16 weak_label
-# ELF-NXX: 10 00 00 00 b 4
+# ELF-NXX: 10 00 00 00 b 0xc <local_label+0xc>
# ELF-N32-NEXT: R_MIPS_PC16 weak_label
# ELF-N64-NEXT: R_MIPS_PC16/R_MIPS_NONE/R_MIPS_NONE weak_label
@@ -67,10 +67,10 @@ local_label:
# MICRO: b global_label # encoding: [0x94,0x00,A,A]
# MICRO: # fixup A - offset: 0, value: global_label, kind: fixup_MICROMIPS_PC16_S1
-# ELF-O32: 10 00 ff ff b 0
+# ELF-O32: 10 00 ff ff b 0x10 <local_label+0x10>
# ELF-O32-NEXT: 00000010: R_MIPS_PC16 global_label
-# ELF-NXX: 10 00 00 00 b 4
+# ELF-NXX: 10 00 00 00 b 0x14 <local_label+0x14>
# ELF-N32-NEXT: R_MIPS_PC16 global_label
# ELF-N64-NEXT: R_MIPS_PC16/R_MIPS_NONE/R_MIPS_NONE global_label
@@ -83,10 +83,10 @@ local_label:
# MICRO: b .text # encoding: [0x94,0x00,A,A]
# MICRO: # fixup A - offset: 0, value: .text, kind: fixup_MICROMIPS_PC16_S1
-# ELF-O32: 10 00 ff f9 b -24 <local_label>
+# ELF-O32: 10 00 ff f9 b 0x0 <local_label>
# ELF-O32-NEXT: 00 00 00 00 nop
-# ELF-NXX: 10 00 ff f9 b -24 <local_label>
+# ELF-NXX: 10 00 ff f9 b 0x0 <local_label>
# ELF-NXX-NEXT: 00 00 00 00 nop
j 1f
@@ -98,9 +98,9 @@ local_label:
# MICRO: b {{.*}}tmp0{{.*}} # encoding: [0x94,0x00,A,A]
# MICRO: # fixup A - offset: 0, value: {{.*}}tmp0{{.*}}, kind: fixup_MICROMIPS_PC16_S1
-# ELF-O32: 10 00 00 04 b 20 <local_label+0x34>
+# ELF-O32: 10 00 00 04 b 0x34 <local_label+0x34>
-# ELF-NXX: 10 00 00 04 b 20 <local_label+0x34>
+# ELF-NXX: 10 00 00 04 b 0x34 <local_label+0x34>
.local forward_local
j forward_local
@@ -112,9 +112,9 @@ local_label:
# MICRO: b forward_local # encoding: [0x94,0x00,A,A]
# MICRO: # fixup A - offset: 0, value: forward_local, kind: fixup_MICROMIPS_PC16_S1
-# ELF-O32: 10 00 00 04 b 20 <forward_local>
+# ELF-O32: 10 00 00 04 b 0x3c <forward_local>
-# ELF-NXX: 10 00 00 04 b 20 <forward_local>
+# ELF-NXX: 10 00 00 04 b 0x3c <forward_local>
j 0x4
@@ -122,9 +122,9 @@ local_label:
# MICRO: b 4 # encoding: [0x94,0x00,0x00,0x02]
-# ELF-O32: 10 00 00 01 b 8
+# ELF-O32: 10 00 00 01 b 0x38 <local_label+0x38>
-# ELF-NXX: 10 00 00 01 b 8
+# ELF-NXX: 10 00 00 01 b 0x38 <local_label+0x38>
.end local_label
diff --git a/llvm/test/MC/Mips/instr-analysis.s b/llvm/test/MC/Mips/instr-analysis.s
index 3ee8df3dd2317..fd63168cbf9d4 100644
--- a/llvm/test/MC/Mips/instr-analysis.s
+++ b/llvm/test/MC/Mips/instr-analysis.s
@@ -2,23 +2,23 @@
# RUN: | llvm-objdump -d - | FileCheck %s
# CHECK: <foo>:
-# CHECK-NEXT: 0: 0c 00 00 02 jal 8 <loc1>
+# CHECK-NEXT: 0: 0c 00 00 02 jal 0x8 <loc1>
# CHECK-NEXT: 4: 00 00 00 00 nop
#
# CHECK: <loc1>:
-# CHECK-NEXT: 8: 0c 00 00 06 jal 24 <loc3>
+# CHECK-NEXT: 8: 0c 00 00 06 jal 0x18 <loc3>
# CHECK-NEXT: c: 00 00 00 00 nop
#
# CHECK: <loc2>:
-# CHECK-NEXT: 10: 10 00 ff fd b -8 <loc1>
+# CHECK-NEXT: 10: 10 00 ff fd b 0x8 <loc1>
# CHECK-NEXT: 14: 00 00 00 00 nop
#
# CHECK: <loc3>:
-# CHECK-NEXT: 18: 10 43 ff fd beq $2, $3, -8 <loc2>
+# CHECK-NEXT: 18: 10 43 ff fd beq $2, $3, 0x10 <loc2>
# CHECK-NEXT: 1c: 00 00 00 00 nop
-# CHECK-NEXT: 20: 04 11 ff f9 bal -24 <loc1>
+# CHECK-NEXT: 20: 04 11 ff f9 bal 0x8 <loc1>
# CHECK-NEXT: 24: 00 00 00 00 nop
-# CHECK-NEXT: 28: 08 00 00 04 j 16 <loc2>
+# CHECK-NEXT: 28: 08 00 00 04 j 0x10 <loc2>
.text
.globl foo
diff --git a/llvm/test/MC/Mips/micromips-el-fixup-data.s b/llvm/test/MC/Mips/micromips-el-fixup-data.s
index 0b9a02f529997..5eacd958c84ee 100644
--- a/llvm/test/MC/Mips/micromips-el-fixup-data.s
+++ b/llvm/test/MC/Mips/micromips-el-fixup-data.s
@@ -16,7 +16,7 @@ main:
addiu $sp, $sp, -16
bnez $9, lab1
-# CHECK: 09 b4 03 00 bnez $9, 10
+# CHECK: 09 b4 03 00 bnez $9, 0xe <lab1>
addu $zero, $zero, $zero
lab1:
diff --git a/llvm/test/MC/Mips/micromips-jump-pc-region.s b/llvm/test/MC/Mips/micromips-jump-pc-region.s
index e531569b48afe..3672933927040 100644
--- a/llvm/test/MC/Mips/micromips-jump-pc-region.s
+++ b/llvm/test/MC/Mips/micromips-jump-pc-region.s
@@ -6,10 +6,10 @@
# Force us into the second 256 MB region with a non-zero instruction index
.org 256*1024*1024 + 12
# CHECK-LABEL: 1000000c <foo>:
-# CHECK-NEXT: 1000000c: d4 00 00 06 j 12 <foo>
-# CHECK-NEXT: 10000010: f4 00 00 08 jal 16 <foo+0x4>
-# CHECK-NEXT: 10000014: f0 00 00 05 jalx 20 <foo+0x8>
-# CHECK-NEXT: 10000018: 74 00 00 0c jals 24 <foo+0xc>
+# CHECK-NEXT: 1000000c: d4 00 00 06 j 0xc <foo>
+# CHECK-NEXT: 10000010: f4 00 00 08 jal 0x10 <foo+0x4>
+# CHECK-NEXT: 10000014: f0 00 00 05 jalx 0x14 <foo+0x8>
+# CHECK-NEXT: 10000018: 74 00 00 0c jals 0x18 <foo+0xc>
foo:
j 12
jal 16
diff --git a/llvm/test/MC/Mips/micromips-neg-offset.s b/llvm/test/MC/Mips/micromips-neg-offset.s
index e821474c35a5b..e51c9b83e56fc 100644
--- a/llvm/test/MC/Mips/micromips-neg-offset.s
+++ b/llvm/test/MC/Mips/micromips-neg-offset.s
@@ -4,9 +4,9 @@
# RUN: -mattr=micromips -mcpu=mips32r6 %s -o - \
# RUN: | llvm-objdump -d --mattr=micromips - | FileCheck %s
-# CHECK: 0: 8f 7e beqzc16 $6, -4
-# CHECK: 2: cf fe bc16 -4
-# CHECK: 4: b7 ff ff fe balc -4
+# CHECK: 0: 8f 7e beqzc16 $6, 0xfffffffc <.text+0xfffffffffffffffc>
+# CHECK: 2: cf fe bc16 0xfffffffe <.text+0xfffffffffffffffe>
+# CHECK: 4: b7 ff ff fe balc 0x0 <.text>
beqz16 $6, -4
b16 -4
diff --git a/llvm/test/MC/Mips/mips-jump-pc-region.s b/llvm/test/MC/Mips/mips-jump-pc-region.s
index 66a0b73d77df6..d5fb6a73009c3 100644
--- a/llvm/test/MC/Mips/mips-jump-pc-region.s
+++ b/llvm/test/MC/Mips/mips-jump-pc-region.s
@@ -8,9 +8,9 @@
# Force us into the second 256 MB region with a non-zero instruction index
.org 256*1024*1024 + 12
# CHECK-LABEL: 1000000c <foo>:
-# CHECK-NEXT: 1000000c: 08 00 00 03 j 12 <foo>
-# CHECK-NEXT: 10000010: 0c 00 00 04 jal 16 <foo+0x4>
-# CHECK-NEXT: 10000014: 74 00 00 05 jalx 20 <foo+0x8>
+# CHECK-NEXT: 1000000c: 08 00 00 03 j 0xc <foo>
+# CHECK-NEXT: 10000010: 0c 00 00 04 jal 0x10 <foo+0x4>
+# CHECK-NEXT: 10000014: 74 00 00 05 jalx 0x14 <foo+0x8>
foo:
j 12
jal 16
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