[PATCH] D123857: [CodeGen] Add separate UseList for each ResNo of SDNode

[Daniil Kovalev via Phabricator via llvm-commits]

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It is now a common pattern to iterate over SDNode uses corresponsing to a
specific ResNo with code like this:

  for (auto UI = N->use_begin(), UE = N->use_end(); UI != UE; ++UI) {
    if (UI.getUse().getResNo() != SomeValue)
      continue;
    // ...
  }

It results in performance decrease when we have many ResNo's and have to
iterate over all their uses instead of only needed ones. A perfect example of
that is `SDNode::hasNUsesOfValue`.

This patch adds new fields to SDNode and SDUse responsible for use lists for
each ResNo separately. Keeping in mind that it increases those classes sizes,
performance testing with llvm-test-suite was done, and no noticeable issues
with compile and link timings were detected. On the contrary, when compiling
IR like this, we get a significant performance enhancement (78.4s -> 14.7s on
my machine).

  %struct.large = type { [65535 x i8] }
  define void @foo(%struct.large %s, %struct.large* %p) {
    store %struct.large %s, %struct.large* %p, align 1
    ret void
  }

This patch will be followed by another one fixing failing assertion when
compiling code with large structs (which was the root cause of investigation
resulting in current change).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D123857

Files:
  llvm/include/llvm/CodeGen/SelectionDAGNodes.h
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
  llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
  llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp

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