[PATCH] D123449: [AArch64][SelectionDAG] Refactor to support more scalable vector extending stores
Allen zhong via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 15 04:12:42 PDT 2022
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Allen marked an inline comment as done.
Closed by commit rG49cb4fef02e6: [AArch64][SelectionDAG] Refactor to support more scalable vector extending… (authored by Allen).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D123449/new/
https://reviews.llvm.org/D123449
Files:
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1177,22 +1177,11 @@
setOperationAction(ISD::MSCATTER, VT, Custom);
}
- for (MVT VT : MVT::fp_scalable_vector_valuetypes()) {
- for (MVT InnerVT : MVT::fp_scalable_vector_valuetypes()) {
- // Avoid marking truncating FP stores as legal to prevent the
- // DAGCombiner from creating unsupported truncating stores.
+ // Firstly, exclude all scalable vector extending loads/truncating stores,
+ // include both integer and floating scalable vector.
+ for (MVT VT : MVT::scalable_vector_valuetypes()) {
+ for (MVT InnerVT : MVT::scalable_vector_valuetypes()) {
setTruncStoreAction(VT, InnerVT, Expand);
- // SVE does not have floating-point extending loads.
- setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
- setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
- setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
- }
- }
-
- // Firstly, exclude all scalable vector extending loads/truncating stores.
- for (MVT VT : MVT::integer_scalable_vector_valuetypes()) {
- for (MVT InnerVT : MVT::integer_scalable_vector_valuetypes()) {
- // TODO: truncating stores should also be exclude
setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
@@ -1200,6 +1189,12 @@
}
// Then, selectively enable those which we directly support.
+ setTruncStoreAction(MVT::nxv2i64, MVT::nxv2i8, Legal);
+ setTruncStoreAction(MVT::nxv2i64, MVT::nxv2i16, Legal);
+ setTruncStoreAction(MVT::nxv2i64, MVT::nxv2i32, Legal);
+ setTruncStoreAction(MVT::nxv4i32, MVT::nxv4i8, Legal);
+ setTruncStoreAction(MVT::nxv4i32, MVT::nxv4i16, Legal);
+ setTruncStoreAction(MVT::nxv8i16, MVT::nxv8i8, Legal);
for (auto Op : {ISD::ZEXTLOAD, ISD::SEXTLOAD, ISD::EXTLOAD}) {
setLoadExtAction(Op, MVT::nxv2i64, MVT::nxv2i8, Legal);
setLoadExtAction(Op, MVT::nxv2i64, MVT::nxv2i16, Legal);
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