[llvm] f097885 - [gn build] (manually) port 6d45558c1a05d (MipsGenPostLegalizeGICombiner)
Nico Weber via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 15 04:05:25 PDT 2022
Author: Nico Weber
Date: 2022-04-15T07:05:15-04:00
New Revision: f097885b07435bb6cd64440ed23c60660024285e
URL: https://github.com/llvm/llvm-project/commit/f097885b07435bb6cd64440ed23c60660024285e
DIFF: https://github.com/llvm/llvm-project/commit/f097885b07435bb6cd64440ed23c60660024285e.diff
LOG: [gn build] (manually) port 6d45558c1a05d (MipsGenPostLegalizeGICombiner)
Added:
Modified:
llvm/utils/gn/secondary/llvm/lib/Target/Mips/BUILD.gn
Removed:
################################################################################
diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/Mips/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/Mips/BUILD.gn
index 055f2ae5aaae0..d030c5e040098 100644
--- a/llvm/utils/gn/secondary/llvm/lib/Target/Mips/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/lib/Target/Mips/BUILD.gn
@@ -30,6 +30,15 @@ tablegen("MipsGenMCPseudoLowering") {
td_file = "Mips.td"
}
+tablegen("MipsGenPostLegalizeGICombiner") {
+ visibility = [ ":LLVMMipsCodeGen" ]
+ args = [
+ "-gen-global-isel-combiner",
+ "-combiners=MipsPostLegalizerCombinerHelper",
+ ]
+ td_file = "Mips.td"
+}
+
tablegen("MipsGenRegisterBank") {
visibility = [ ":LLVMMipsCodeGen" ]
args = [ "-gen-register-bank" ]
@@ -43,6 +52,7 @@ static_library("LLVMMipsCodeGen") {
":MipsGenFastISel",
":MipsGenGlobalISel",
":MipsGenMCPseudoLowering",
+ ":MipsGenPostLegalizeGICombiner",
":MipsGenRegisterBank",
"MCTargetDesc",
"TargetInfo",
@@ -88,6 +98,7 @@ static_library("LLVMMipsCodeGen") {
"MipsMulMulBugPass.cpp",
"MipsOptimizePICCall.cpp",
"MipsOs16.cpp",
+ "MipsPostLegalizerCombiner.cpp",
"MipsPreLegalizerCombiner.cpp",
"MipsRegisterBankInfo.cpp",
"MipsRegisterInfo.cpp",
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