[PATCH] D123525: [AMDGPU] On gfx908, reserve VGPR for AGPR copy based on register budget.

[Mahesha S via Phabricator via llvm-commits]

hsmhsm updated this revision to Diff 423060.
hsmhsm added a comment.

Rebase to latest trunk and to D123809 <https://reviews.llvm.org/D123809>.

Since the lit test for the function @max_5regs_used_8a() within spill-agpr.ll asserts for
gfx908 when used only 5 vgprs, I could not find any other way, but had to move this function
from spill-agpr.ll to spill-agpr-to-memory-gfx90a.ll and spill-agpr-to-memory-gfx908.ll.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123525/new/

https://reviews.llvm.org/D123525

Files:
  llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
  llvm/lib/Target/AMDGPU/SIFrameLowering.h
  llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
  llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
  llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
  llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir
  llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
  llvm/test/CodeGen/AMDGPU/agpr-copy-no-vgprs.mir
  llvm/test/CodeGen/AMDGPU/agpr-copy-sgpr-no-vgprs.mir
  llvm/test/CodeGen/AMDGPU/agpr-remat.ll
  llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx908.mir
  llvm/test/CodeGen/AMDGPU/av_spill_cross_bb_usage.mir
  llvm/test/CodeGen/AMDGPU/pei-build-av-spill.mir
  llvm/test/CodeGen/AMDGPU/pei-build-spill.mir
  llvm/test/CodeGen/AMDGPU/regalloc-introduces-copy-sgpr-to-agpr.mir
  llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir
  llvm/test/CodeGen/AMDGPU/spill-agpr-partially-undef.mir
  llvm/test/CodeGen/AMDGPU/spill-agpr-to-memory-gfx908.ll
  llvm/test/CodeGen/AMDGPU/spill-agpr-to-memory-gfx90a.ll
  llvm/test/CodeGen/AMDGPU/spill-agpr.ll
  llvm/test/CodeGen/AMDGPU/spill-agpr.mir
  llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll