[PATCH] D123801: [DAG] Combine shuffle(bitcast(X), Mask) to bitcast(shuffle(X, Mask'))

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: PowerPC, RKSimon, craig.topper, spatel, nemanjai.
Herald added subscribers: StephenFan, steven.zhang, pengfei, kbarton, hiraditya, kristof.beyls.
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If the mask is made up of elements that form a mask in the higher type we can convert `shuffle(bitcast` into the bitcast type, simplifying the instruction sequence. A v4i32 `2,3,0,1` for example can be treated as a `1,0` v2i64 shuffle. This helps clean up some of the AArch64 concat load combines, along with helping simplify a number of other tests.

The PowerPC combine for v16i8 splat vector loads needed some fixes to keep it working for v16i8 vectors. This improves the handling of v2i64 shuffles to match too, hopefully improving them in general. I'd appreciate careful review of that part though, as I have no idea if it is correct.


https://reviews.llvm.org/D123801

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/AArch64/insert-extend.ll
  llvm/test/CodeGen/ARM/neon-copy.ll
  llvm/test/CodeGen/ARM/vector-DAGCombine.ll
  llvm/test/CodeGen/PowerPC/aix-vsx-splatimm.ll
  llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
  llvm/test/CodeGen/PowerPC/vsx_shuffle_le.ll
  llvm/test/CodeGen/Thumb2/mve-shufflemov.ll
  llvm/test/CodeGen/Thumb2/mve-vld2-post.ll
  llvm/test/CodeGen/Thumb2/mve-vld2.ll
  llvm/test/CodeGen/Thumb2/mve-vst3.ll
  llvm/test/CodeGen/Thumb2/mve-vst4.ll
  llvm/test/CodeGen/X86/avx-vbroadcast.ll
  llvm/test/CodeGen/X86/oddshuffles.ll
  llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-2.ll
  llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll
  llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-4.ll
  llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
  llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
  llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-2.ll
  llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-3.ll
  llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-4.ll
  llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll
  llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-2.ll
  llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-3.ll
  llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
  llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll

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