[llvm] 27a8735 - [AArch64] Add mayRaiseFPException to appropriate instructions
John Brawn via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 14 08:51:47 PDT 2022
Author: John Brawn
Date: 2022-04-14T16:51:22+01:00
New Revision: 27a8735a444fb311838f06f8d0d5b10ca9b541f6
URL: https://github.com/llvm/llvm-project/commit/27a8735a444fb311838f06f8d0d5b10ca9b541f6
DIFF: https://github.com/llvm/llvm-project/commit/27a8735a444fb311838f06f8d0d5b10ca9b541f6.diff
LOG: [AArch64] Add mayRaiseFPException to appropriate instructions
This is mostly handled by adding "let mayRaiseFPException = 1" before
the definition of the relevant instruction classes, but there are a
couple of complications:
* When we have a multiclass where currently some instantiations are
of instructions that can raise an exception and others aren't we
need to split that into two multiclasses, one inheriting from the
other using a multiclass parameter to enable exceptions.
* In a couple of places in the globalisel instruction selector we
need to manually set the NoFPExcept flag. There's also another
place that looks like it should need it, but that code is never hit
for those opcodes due to them being handled by the generic
instruction selector, so I've instead just removed them from the
switch.
Differential Revision: https://reviews.llvm.org/D115352
Added:
llvm/test/CodeGen/AArch64/strict-fp-opt.ll
Modified:
llvm/lib/Target/AArch64/AArch64InstrFormats.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
llvm/test/CodeGen/AArch64/GlobalISel/fold-brcond-fcmp.mir
llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir
llvm/test/CodeGen/AArch64/GlobalISel/fold-select.mir
llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-ceil.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-faddp.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-fcmp.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-floor.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-fma.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-fmul-indexed.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-frint.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-round.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-trunc.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-nearbyint.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vector-fcmp.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-sqrt.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-static.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
llvm/test/CodeGen/AArch64/GlobalISel/select.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 38049d4f6344c..e7d37c3ab5d4b 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -4559,6 +4559,7 @@ let Predicates = [HasFPARMv8] in {
// Floating point to integer conversion
//---
+let mayRaiseFPException = 1 in
class BaseFPToIntegerUnscaled<bits<2> type, bits<2> rmode, bits<3> opcode,
RegisterClass srcType, RegisterClass dstType,
string asm, list<dag> pattern>
@@ -4578,7 +4579,7 @@ class BaseFPToIntegerUnscaled<bits<2> type, bits<2> rmode, bits<3> opcode,
let Inst{4-0} = Rd;
}
-let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in
class BaseFPToInteger<bits<2> type, bits<2> rmode, bits<3> opcode,
RegisterClass srcType, RegisterClass dstType,
Operand immType, string asm, list<dag> pattern>
@@ -4700,7 +4701,7 @@ multiclass FPToIntegerScaled<bits<2> rmode, bits<3> opcode, string asm,
// Integer to floating point conversion
//---
-let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
+let mayStore = 0, mayLoad = 0, hasSideEffects = 0, mayRaiseFPException = 1 in
class BaseIntegerToFP<bit isUnsigned,
RegisterClass srcType, RegisterClass dstType,
Operand immType, string asm, list<dag> pattern>
@@ -4718,6 +4719,7 @@ class BaseIntegerToFP<bit isUnsigned,
let Inst{4-0} = Rd;
}
+let mayRaiseFPException = 1 in
class BaseIntegerToFPUnscaled<bit isUnsigned,
RegisterClass srcType, RegisterClass dstType,
ValueType dvt, string asm, SDPatternOperator node>
@@ -4954,6 +4956,7 @@ multiclass UnscaledConversion<string asm> {
// Floating point conversion
//---
+let mayRaiseFPException = 1 in
class BaseFPConversion<bits<2> type, bits<2> opcode, RegisterClass dstType,
RegisterClass srcType, string asm, list<dag> pattern>
: I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "", pattern>,
@@ -5016,8 +5019,9 @@ class BaseSingleOperandFPData<bits<6> opcode, RegisterClass regtype,
}
multiclass SingleOperandFPData<bits<4> opcode, string asm,
- SDPatternOperator node = null_frag> {
-
+ SDPatternOperator node = null_frag,
+ int fpexceptions = 1> {
+ let mayRaiseFPException = fpexceptions in {
def Hr : BaseSingleOperandFPData<{0b00,opcode}, FPR16, f16, asm, node> {
let Inst{23-22} = 0b11; // 16-bit size flag
let Predicates = [HasFullFP16];
@@ -5030,8 +5034,14 @@ multiclass SingleOperandFPData<bits<4> opcode, string asm,
def Dr : BaseSingleOperandFPData<{0b00,opcode}, FPR64, f64, asm, node> {
let Inst{23-22} = 0b01; // 64-bit size flag
}
+ }
}
+multiclass SingleOperandFPDataNoException<bits<4> opcode, string asm,
+ SDPatternOperator node = null_frag>
+ : SingleOperandFPData<opcode, asm, node, 0>;
+
+let mayRaiseFPException = 1 in
multiclass SingleOperandFPNo16<bits<6> opcode, string asm,
SDPatternOperator node = null_frag>{
@@ -5052,7 +5062,7 @@ multiclass FRIntNNT<bits<2> opcode, string asm, SDPatternOperator node = null_fr
// Two operand floating point data processing
//---
-let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in
class BaseTwoOperandFPData<bits<4> opcode, RegisterClass regtype,
string asm, list<dag> pat>
: I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
@@ -5116,6 +5126,7 @@ multiclass TwoOperandFPDataNeg<bits<4> opcode, string asm,
// Three operand floating point data processing
//---
+let mayRaiseFPException = 1 in
class BaseThreeOperandFPData<bit isNegated, bit isSub,
RegisterClass regtype, string asm, list<dag> pat>
: I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, regtype: $Ra),
@@ -5160,7 +5171,7 @@ multiclass ThreeOperandFPData<bit isNegated, bit isSub,string asm,
// Floating point data comparisons
//---
-let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in
class BaseOneOperandFPComparison<bit signalAllNans,
RegisterClass regtype, string asm,
list<dag> pat>
@@ -5179,7 +5190,7 @@ class BaseOneOperandFPComparison<bit signalAllNans,
let PostEncoderMethod = "fixOneOperandFPComparison";
}
-let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in
class BaseTwoOperandFPComparison<bit signalAllNans, RegisterClass regtype,
string asm, list<dag> pat>
: I<(outs), (ins regtype:$Rn, regtype:$Rm), asm, "\t$Rn, $Rm", "", pat>,
@@ -5236,7 +5247,7 @@ multiclass FPComparison<bit signalAllNans, string asm,
// Floating point conditional comparisons
//---
-let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in
class BaseFPCondComparison<bit signalAllNans, RegisterClass regtype,
string mnemonic, list<dag> pat>
: I<(outs), (ins regtype:$Rn, regtype:$Rm, imm32_0_15:$nzcv, ccode:$cond),
@@ -5562,6 +5573,7 @@ multiclass SIMDThreeSameVectorB<bit U, bits<5> opc, string asm,
}
// As above, but only floating point elements supported.
+let mayRaiseFPException = 1 in
multiclass SIMDThreeSameVectorFP<bit U, bit S, bits<3> opc,
string asm, SDPatternOperator OpNode> {
let Predicates = [HasNEON, HasFullFP16] in {
@@ -5583,6 +5595,7 @@ multiclass SIMDThreeSameVectorFP<bit U, bit S, bits<3> opc,
[(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
}
+let mayRaiseFPException = 1 in
multiclass SIMDThreeSameVectorFPCmp<bit U, bit S, bits<3> opc,
string asm,
SDPatternOperator OpNode> {
@@ -5605,6 +5618,7 @@ multiclass SIMDThreeSameVectorFPCmp<bit U, bit S, bits<3> opc,
[(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
}
+let mayRaiseFPException = 1 in
multiclass SIMDThreeSameVectorFPTied<bit U, bit S, bits<3> opc,
string asm, SDPatternOperator OpNode> {
let Predicates = [HasNEON, HasFullFP16] in {
@@ -5632,6 +5646,7 @@ multiclass SIMDThreeSameVectorFPTied<bit U, bit S, bits<3> opc,
}
// As above, but D and B sized elements unsupported.
+let mayRaiseFPException = 1 in
multiclass SIMDThreeSameVectorHS<bit U, bits<5> opc, string asm,
SDPatternOperator OpNode> {
def v4i16 : BaseSIMDThreeSameVector<0, U, 0b011, opc, V64,
@@ -5736,6 +5751,7 @@ multiclass SIMDThreeSameVectorDot<bit U, bit Mixed, string asm, SDPatternOperato
// ARMv8.2-A Fused Multiply Add-Long Instructions (Vector): These instructions
// select inputs from 4H vectors and accumulate outputs to a 2S vector (or from
// 8H to 4S, when Q=1).
+let mayRaiseFPException = 1 in
class BaseSIMDThreeSameVectorFML<bit Q, bit U, bit b13, bits<3> size, string asm, string kind1,
string kind2, RegisterOperand RegType,
ValueType AccumType, ValueType InputType,
@@ -6004,7 +6020,9 @@ multiclass SIMDTwoVectorBH<bit U, bits<5> opc, string asm,
// Supports H, S and D element sizes, uses high bit of the size field
// as an extra opcode bit.
multiclass SIMDTwoVectorFP<bit U, bit S, bits<5> opc, string asm,
- SDPatternOperator OpNode> {
+ SDPatternOperator OpNode,
+ int fpexceptions = 1> {
+ let mayRaiseFPException = fpexceptions in {
let Predicates = [HasNEON, HasFullFP16] in {
def v4f16 : BaseSIMDTwoSameVector<0, U, {S,1}, opc, 0b11, V64,
asm, ".4h", ".4h",
@@ -6022,9 +6040,15 @@ multiclass SIMDTwoVectorFP<bit U, bit S, bits<5> opc, string asm,
def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b00, V128,
asm, ".2d", ".2d",
[(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
+ }
}
+multiclass SIMDTwoVectorFPNoException<bit U, bit S, bits<5> opc, string asm,
+ SDPatternOperator OpNode>
+ : SIMDTwoVectorFP<U, S, opc, asm, OpNode, 0>;
+
// Supports only S and D element sizes
+let mayRaiseFPException = 1 in
multiclass SIMDTwoVectorSD<bit U, bits<5> opc, string asm,
SDPatternOperator OpNode = null_frag> {
@@ -6054,7 +6078,7 @@ multiclass SIMDTwoVectorS<bit U, bit S, bits<5> opc, string asm,
[(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
}
-
+let mayRaiseFPException = 1 in
multiclass SIMDTwoVectorFPToInt<bit U, bit S, bits<5> opc, string asm,
SDPatternOperator OpNode> {
let Predicates = [HasNEON, HasFullFP16] in {
@@ -6076,6 +6100,7 @@ multiclass SIMDTwoVectorFPToInt<bit U, bit S, bits<5> opc, string asm,
[(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
}
+let mayRaiseFPException = 1 in
multiclass SIMDTwoVectorIntToFP<bit U, bit S, bits<5> opc, string asm,
SDPatternOperator OpNode> {
let Predicates = [HasNEON, HasFullFP16] in {
@@ -6227,6 +6252,7 @@ multiclass SIMDCmpTwoVector<bit U, bits<5> opc, string asm,
multiclass SIMDFPCmpTwoVector<bit U, bit S, bits<5> opc,
string asm, SDNode OpNode> {
+ let mayRaiseFPException = 1 in {
let Predicates = [HasNEON, HasFullFP16] in {
def v4i16rz : BaseSIMDCmpTwoVector<0, U, {S,1}, 0b11, opc, V64,
asm, ".4h", "0.0",
@@ -6244,6 +6270,7 @@ multiclass SIMDFPCmpTwoVector<bit U, bit S, bits<5> opc,
def v2i64rz : BaseSIMDCmpTwoVector<1, U, {S,1}, 0b00, opc, V128,
asm, ".2d", "0.0",
v2i64, v2f64, OpNode>;
+ }
let Predicates = [HasNEON, HasFullFP16] in {
def : InstAlias<asm # "\t$Vd.4h, $Vn.4h, #0",
@@ -6271,7 +6298,7 @@ multiclass SIMDFPCmpTwoVector<bit U, bit S, bits<5> opc,
(!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
}
-let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in
class BaseSIMDFPCvtTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
RegisterOperand outtype, RegisterOperand intype,
string asm, string VdTy, string VnTy,
@@ -6293,7 +6320,7 @@ class BaseSIMDFPCvtTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
let Inst{4-0} = Rd;
}
-let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in
class BaseSIMDFPCvtTwoVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
RegisterOperand outtype, RegisterOperand intype,
string asm, string VdTy, string VnTy,
@@ -6894,7 +6921,7 @@ multiclass SIMDThreeScalarHSTied<bit U, bit R, bits<5> opc, string asm> {
multiclass SIMDFPThreeScalar<bit U, bit S, bits<3> opc, string asm,
SDPatternOperator OpNode = null_frag,
Predicate pred = HasNEON> {
- let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
+ let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in {
let Predicates = [pred] in {
def NAME#64 : BaseSIMDThreeScalar<U, {S,0b11}, {0b11,opc}, FPR64, asm,
[(set (f64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
@@ -6913,7 +6940,7 @@ multiclass SIMDFPThreeScalar<bit U, bit S, bits<3> opc, string asm,
multiclass SIMDThreeScalarFPCmp<bit U, bit S, bits<3> opc, string asm,
SDPatternOperator OpNode = null_frag> {
- let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
+ let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in {
def NAME#64 : BaseSIMDThreeScalar<U, {S,0b11}, {0b11,opc}, FPR64, asm,
[(set (i64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
def NAME#32 : BaseSIMDThreeScalar<U, {S,0b01}, {0b11,opc}, FPR32, asm,
@@ -7043,6 +7070,7 @@ class BaseSIMDCmpTwoScalar<bit U, bits<2> size, bits<2> size2, bits<5> opcode,
let Inst{4-0} = Rd;
}
+let mayRaiseFPException = 1 in
class SIMDInexactCvtTwoScalar<bits<5> opcode, string asm>
: I<(outs FPR32:$Rd), (ins FPR64:$Rn), asm, "\t$Rd, $Rn", "",
[(set (f32 FPR32:$Rd), (int_aarch64_sisd_fcvtxn (f64 FPR64:$Rn)))]>,
@@ -7066,11 +7094,13 @@ multiclass SIMDCmpTwoScalarD<bit U, bits<5> opc, string asm,
multiclass SIMDFPCmpTwoScalar<bit U, bit S, bits<5> opc, string asm,
SDPatternOperator OpNode> {
+ let mayRaiseFPException = 1 in {
def v1i64rz : BaseSIMDCmpTwoScalar<U, {S,1}, 0b00, opc, FPR64, asm, "0.0">;
def v1i32rz : BaseSIMDCmpTwoScalar<U, {S,0}, 0b00, opc, FPR32, asm, "0.0">;
let Predicates = [HasNEON, HasFullFP16] in {
def v1i16rz : BaseSIMDCmpTwoScalar<U, {S,1}, 0b11, opc, FPR16, asm, "0.0">;
}
+ }
def : InstAlias<asm # "\t$Rd, $Rn, #0",
(!cast<Instruction>(NAME # v1i64rz) FPR64:$Rd, FPR64:$Rn), 0>;
@@ -7094,6 +7124,7 @@ multiclass SIMDTwoScalarD<bit U, bits<5> opc, string asm,
(!cast<Instruction>(NAME # "v1i64") FPR64:$Rn)>;
}
+let mayRaiseFPException = 1 in
multiclass SIMDFPTwoScalar<bit U, bit S, bits<5> opc, string asm,
Predicate pred = HasNEON> {
let Predicates = [pred] in {
@@ -7105,6 +7136,7 @@ multiclass SIMDFPTwoScalar<bit U, bit S, bits<5> opc, string asm,
}
}
+let mayRaiseFPException = 1 in
multiclass SIMDFPTwoScalarCVT<bit U, bit S, bits<5> opc, string asm,
SDPatternOperator OpNode> {
def v1i64 : BaseSIMDTwoScalar<U, {S,1}, 0b00, opc, FPR64, FPR64, asm,
@@ -7187,6 +7219,7 @@ multiclass SIMDPairwiseScalarD<bit U, bits<5> opc, string asm> {
asm, ".2d">;
}
+let mayRaiseFPException = 1 in
multiclass SIMDFPPairwiseScalar<bit S, bits<5> opc, string asm> {
let Predicates = [HasNEON, HasFullFP16] in {
def v2i16p : BaseSIMDPairwiseScalar<0, {S,0}, opc, FPR16Op, V64,
@@ -7250,6 +7283,7 @@ multiclass SIMDAcrossLanesHSD<bit U, bits<5> opcode, string asm> {
asm, ".4s", []>;
}
+let mayRaiseFPException = 1 in
multiclass SIMDFPAcrossLanes<bits<5> opcode, bit sz1, string asm,
Intrinsic intOp> {
let Predicates = [HasNEON, HasFullFP16] in {
@@ -8066,6 +8100,7 @@ multiclass SIMDThreeSameVectorBF16DotI<bit U, string asm> {
".2h", V128, v4f32, v8bf16>;
}
+let mayRaiseFPException = 1 in
class SIMDBF16MLAL<bit Q, string asm, SDPatternOperator OpNode>
: BaseSIMDThreeSameVectorTied<Q, 0b1, 0b110, 0b11111, V128, asm, ".4s",
[(set (v4f32 V128:$dst), (OpNode (v4f32 V128:$Rd),
@@ -8074,6 +8109,7 @@ class SIMDBF16MLAL<bit Q, string asm, SDPatternOperator OpNode>
let AsmString = !strconcat(asm, "{\t$Rd.4s, $Rn.8h, $Rm.8h}");
}
+let mayRaiseFPException = 1 in
class SIMDBF16MLALIndex<bit Q, string asm, SDPatternOperator OpNode>
: I<(outs V128:$dst),
(ins V128:$Rd, V128:$Rn, V128_lo:$Rm, VectorIndexH:$idx), asm,
@@ -8113,18 +8149,21 @@ class SIMDThreeSameVectorBF16MatrixMul<string asm>
", $Rm", ".8h", "}");
}
+let mayRaiseFPException = 1 in
class SIMD_BFCVTN
: BaseSIMDMixedTwoVector<0, 0, 0b10, 0b10110, V128, V128,
"bfcvtn", ".4h", ".4s",
[(set (v8bf16 V128:$Rd),
(int_aarch64_neon_bfcvtn (v4f32 V128:$Rn)))]>;
+let mayRaiseFPException = 1 in
class SIMD_BFCVTN2
: BaseSIMDMixedTwoVectorTied<1, 0, 0b10, 0b10110, V128, V128,
"bfcvtn2", ".8h", ".4s",
[(set (v8bf16 V128:$dst),
(int_aarch64_neon_bfcvtn2 (v8bf16 V128:$Rd), (v4f32 V128:$Rn)))]>;
+let mayRaiseFPException = 1 in
class BF16ToSinglePrecision<string asm>
: I<(outs FPR16:$Rd), (ins FPR32:$Rn), asm, "\t$Rd, $Rn", "",
[(set (bf16 FPR16:$Rd), (int_aarch64_neon_bfcvt (f32 FPR32:$Rn)))]>,
@@ -8178,6 +8217,7 @@ multiclass SIMDThreeSameVectorDotIndex<bit U, bit Mixed, bits<2> size, string as
}
// ARMv8.2-A Fused Multiply Add-Long Instructions (Indexed)
+let mayRaiseFPException = 1 in
class BaseSIMDThreeSameVectorFMLIndex<bit Q, bit U, bits<4> opc, string asm,
string dst_kind, string lhs_kind,
string rhs_kind, RegisterOperand RegType,
@@ -8205,6 +8245,7 @@ multiclass SIMDThreeSameVectorFMLIndex<bit U, bits<4> opc, string asm,
V128, v4f32, v8f16, OpNode>;
}
+let mayRaiseFPException = 1 in
multiclass SIMDFPIndexed<bit U, bits<4> opc, string asm,
SDPatternOperator OpNode> {
let Predicates = [HasNEON, HasFullFP16] in {
@@ -8387,6 +8428,7 @@ multiclass SIMDFPIndexedTiedPatterns<string INST, SDPatternOperator OpNode> {
V128:$Rm, VectorIndexD:$idx)>;
}
+let mayRaiseFPException = 1 in
multiclass SIMDFPIndexedTied<bit U, bits<4> opc, string asm> {
let Predicates = [HasNEON, HasFullFP16] in {
def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b00, opc, V64, V64,
@@ -10689,7 +10731,7 @@ def complexrotateopodd : Operand<i32>, TImmLeaf<i32, [{ return Imm >= 0 && Imm <
let ParserMatchClass = ComplexRotationOperand<180, 90, "Odd">;
let PrintMethod = "printComplexRotationOp<180, 90>";
}
-let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in
class BaseSIMDThreeSameVectorComplex<bit Q, bit U, bits<2> size, bits<3> opcode,
RegisterOperand regtype, Operand rottype,
string asm, string kind, list<dag> pattern>
@@ -10760,7 +10802,7 @@ multiclass SIMDThreeSameVectorComplexHSD<bit U, bits<3> opcode, Operand rottype,
}
}
-let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in
class BaseSIMDThreeSameVectorTiedComplex<bit Q, bit U, bits<2> size,
bits<3> opcode,
RegisterOperand regtype,
@@ -10832,7 +10874,7 @@ multiclass SIMDThreeSameVectorTiedComplexHSD<bit U, bits<3> opcode,
}
}
-let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1 in
class BaseSIMDIndexedTiedComplex<bit Q, bit U, bit Scalar, bits<2> size,
bit opc1, bit opc2, RegisterOperand dst_reg,
RegisterOperand lhs_reg,
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index e2a4581201bda..d626bf86f740f 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -3972,9 +3972,9 @@ defm FCVT : FPConversion<"fcvt">;
// Floating point single operand instructions.
//===----------------------------------------------------------------------===//
-defm FABS : SingleOperandFPData<0b0001, "fabs", fabs>;
-defm FMOV : SingleOperandFPData<0b0000, "fmov">;
-defm FNEG : SingleOperandFPData<0b0010, "fneg", fneg>;
+defm FABS : SingleOperandFPDataNoException<0b0001, "fabs", fabs>;
+defm FMOV : SingleOperandFPDataNoException<0b0000, "fmov">;
+defm FNEG : SingleOperandFPDataNoException<0b0010, "fneg", fneg>;
defm FRINTA : SingleOperandFPData<0b1100, "frinta", any_fround>;
defm FRINTI : SingleOperandFPData<0b1111, "frinti", any_fnearbyint>;
defm FRINTM : SingleOperandFPData<0b1010, "frintm", any_ffloor>;
@@ -4216,7 +4216,7 @@ defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", AArch64cmgtz>;
defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", AArch64cmlez>;
defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", AArch64cmltz>;
defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
-defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>;
+defm FABS : SIMDTwoVectorFPNoException<0, 1, 0b01111, "fabs", fabs>;
def : Pat<(v8i8 (AArch64vashr (v8i8 V64:$Rn), (i32 7))),
(CMLTv8i8rz V64:$Rn)>;
@@ -4299,7 +4299,7 @@ def : Pat<(v2i32 (int_aarch64_neon_fcvtzu v2f32:$Rn)), (FCVTZUv2f32 $Rn)>;
def : Pat<(v4i32 (int_aarch64_neon_fcvtzu v4f32:$Rn)), (FCVTZUv4f32 $Rn)>;
def : Pat<(v2i64 (int_aarch64_neon_fcvtzu v2f64:$Rn)), (FCVTZUv2f64 $Rn)>;
-defm FNEG : SIMDTwoVectorFP<1, 1, 0b01111, "fneg", fneg>;
+defm FNEG : SIMDTwoVectorFPNoException<1, 1, 0b01111, "fneg", fneg>;
defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_aarch64_neon_frecpe>;
defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", any_fround>;
defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", any_fnearbyint>;
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index b215678d2e436..2b7e4eb3e7f3b 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -3050,10 +3050,6 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
}
}
LLVM_FALLTHROUGH;
- case TargetOpcode::G_FADD:
- case TargetOpcode::G_FSUB:
- case TargetOpcode::G_FMUL:
- case TargetOpcode::G_FDIV:
case TargetOpcode::G_OR: {
// Reject the various things we don't support yet.
if (unsupportedBinOp(I, RBI, MRI, TRI))
@@ -3376,6 +3372,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
I.setDesc(TII.get(NewOpc));
constrainSelectedInstRegOperands(I, TII, TRI, RBI);
+ I.setFlags(MachineInstr::NoFPExcept);
return true;
}
@@ -4701,6 +4698,7 @@ AArch64InstructionSelector::emitFPCompare(Register LHS, Register RHS,
// Partially build the compare. Decide if we need to add a use for the
// third operand based off whether or not we're comparing against 0.0.
auto CmpMI = MIRBuilder.buildInstr(CmpOpc).addUse(LHS);
+ CmpMI.setMIFlags(MachineInstr::NoFPExcept);
if (!ShouldUseImm)
CmpMI.addUse(RHS);
constrainSelectedInstRegOperands(*CmpMI, TII, TRI, RBI);
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/fold-brcond-fcmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/fold-brcond-fcmp.mir
index 9987e9e96e960..139af980a25c7 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/fold-brcond-fcmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/fold-brcond-fcmp.mir
@@ -20,7 +20,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %cmp_lhs:fpr32 = COPY $s0
; CHECK-NEXT: %cmp_rhs:fpr32 = COPY $s1
- ; CHECK-NEXT: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+ ; CHECK-NEXT: nofpexcept FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
; CHECK-NEXT: Bcc 0, %bb.2, implicit $nzcv
; CHECK-NEXT: B %bb.1
; CHECK-NEXT: {{ $}}
@@ -62,7 +62,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %cmp_lhs:fpr32 = COPY $s0
; CHECK-NEXT: %cmp_rhs:fpr32 = COPY $s1
- ; CHECK-NEXT: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+ ; CHECK-NEXT: nofpexcept FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
; CHECK-NEXT: Bcc 12, %bb.2, implicit $nzcv
; CHECK-NEXT: B %bb.1
; CHECK-NEXT: {{ $}}
@@ -104,7 +104,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %cmp_lhs:fpr32 = COPY $s0
; CHECK-NEXT: %cmp_rhs:fpr32 = COPY $s1
- ; CHECK-NEXT: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+ ; CHECK-NEXT: nofpexcept FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
; CHECK-NEXT: Bcc 10, %bb.2, implicit $nzcv
; CHECK-NEXT: B %bb.1
; CHECK-NEXT: {{ $}}
@@ -146,7 +146,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %cmp_lhs:fpr32 = COPY $s0
; CHECK-NEXT: %cmp_rhs:fpr32 = COPY $s1
- ; CHECK-NEXT: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+ ; CHECK-NEXT: nofpexcept FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
; CHECK-NEXT: Bcc 4, %bb.2, implicit $nzcv
; CHECK-NEXT: B %bb.1
; CHECK-NEXT: {{ $}}
@@ -188,7 +188,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %cmp_lhs:fpr32 = COPY $s0
; CHECK-NEXT: %cmp_rhs:fpr32 = COPY $s1
- ; CHECK-NEXT: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+ ; CHECK-NEXT: nofpexcept FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
; CHECK-NEXT: Bcc 9, %bb.2, implicit $nzcv
; CHECK-NEXT: B %bb.1
; CHECK-NEXT: {{ $}}
@@ -230,7 +230,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %cmp_lhs:fpr32 = COPY $s0
; CHECK-NEXT: %cmp_rhs:fpr32 = COPY $s1
- ; CHECK-NEXT: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+ ; CHECK-NEXT: nofpexcept FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
; CHECK-NEXT: Bcc 4, %bb.2, implicit $nzcv
; CHECK-NEXT: Bcc 12, %bb.2, implicit $nzcv
; CHECK-NEXT: B %bb.1
@@ -273,7 +273,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %cmp_lhs:fpr32 = COPY $s0
; CHECK-NEXT: %cmp_rhs:fpr32 = COPY $s1
- ; CHECK-NEXT: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+ ; CHECK-NEXT: nofpexcept FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
; CHECK-NEXT: Bcc 7, %bb.2, implicit $nzcv
; CHECK-NEXT: B %bb.1
; CHECK-NEXT: {{ $}}
@@ -315,7 +315,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %cmp_lhs:fpr32 = COPY $s0
; CHECK-NEXT: %cmp_rhs:fpr32 = COPY $s1
- ; CHECK-NEXT: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+ ; CHECK-NEXT: nofpexcept FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
; CHECK-NEXT: Bcc 6, %bb.2, implicit $nzcv
; CHECK-NEXT: B %bb.1
; CHECK-NEXT: {{ $}}
@@ -357,7 +357,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %cmp_lhs:fpr32 = COPY $s0
; CHECK-NEXT: %cmp_rhs:fpr32 = COPY $s1
- ; CHECK-NEXT: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+ ; CHECK-NEXT: nofpexcept FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
; CHECK-NEXT: Bcc 0, %bb.2, implicit $nzcv
; CHECK-NEXT: Bcc 6, %bb.2, implicit $nzcv
; CHECK-NEXT: B %bb.1
@@ -400,7 +400,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %cmp_lhs:fpr32 = COPY $s0
; CHECK-NEXT: %cmp_rhs:fpr32 = COPY $s1
- ; CHECK-NEXT: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+ ; CHECK-NEXT: nofpexcept FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
; CHECK-NEXT: Bcc 8, %bb.2, implicit $nzcv
; CHECK-NEXT: B %bb.1
; CHECK-NEXT: {{ $}}
@@ -442,7 +442,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %cmp_lhs:fpr32 = COPY $s0
; CHECK-NEXT: %cmp_rhs:fpr32 = COPY $s1
- ; CHECK-NEXT: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+ ; CHECK-NEXT: nofpexcept FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
; CHECK-NEXT: Bcc 5, %bb.2, implicit $nzcv
; CHECK-NEXT: B %bb.1
; CHECK-NEXT: {{ $}}
@@ -484,7 +484,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %cmp_lhs:fpr32 = COPY $s0
; CHECK-NEXT: %cmp_rhs:fpr32 = COPY $s1
- ; CHECK-NEXT: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+ ; CHECK-NEXT: nofpexcept FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
; CHECK-NEXT: Bcc 11, %bb.2, implicit $nzcv
; CHECK-NEXT: B %bb.1
; CHECK-NEXT: {{ $}}
@@ -526,7 +526,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %cmp_lhs:fpr32 = COPY $s0
; CHECK-NEXT: %cmp_rhs:fpr32 = COPY $s1
- ; CHECK-NEXT: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+ ; CHECK-NEXT: nofpexcept FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
; CHECK-NEXT: Bcc 13, %bb.2, implicit $nzcv
; CHECK-NEXT: B %bb.1
; CHECK-NEXT: {{ $}}
@@ -568,7 +568,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %cmp_lhs:fpr32 = COPY $s0
; CHECK-NEXT: %cmp_rhs:fpr32 = COPY $s1
- ; CHECK-NEXT: FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
+ ; CHECK-NEXT: nofpexcept FCMPSrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv
; CHECK-NEXT: Bcc 1, %bb.2, implicit $nzcv
; CHECK-NEXT: B %bb.1
; CHECK-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir
index dcf3c94058c0c..1e6dc70c23221 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir
@@ -28,7 +28,7 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
- ; CHECK-NEXT: FCMPSri [[COPY]], implicit-def $nzcv
+ ; CHECK-NEXT: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY [[CSINCWr]]
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
@@ -65,9 +65,9 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
- ; CHECK-NEXT: FCMPSri [[COPY]], implicit-def $nzcv
+ ; CHECK-NEXT: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv
; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 0, implicit $nzcv
- ; CHECK-NEXT: FCMPSri [[COPY]], implicit-def $nzcv
+ ; CHECK-NEXT: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv
; CHECK-NEXT: [[FCSELSrrr1:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 0, implicit $nzcv
; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
; CHECK-NEXT: $s1 = COPY [[FCSELSrrr1]]
@@ -133,7 +133,7 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
- ; CHECK-NEXT: FCMPSri [[COPY]], implicit-def $nzcv
+ ; CHECK-NEXT: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv
; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[FMOVS0_]], [[COPY1]], 0, implicit $nzcv
; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
@@ -164,7 +164,7 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
- ; CHECK-NEXT: FCMPSri [[COPY]], implicit-def $nzcv
+ ; CHECK-NEXT: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
@@ -201,7 +201,7 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
- ; CHECK-NEXT: FCMPSri [[COPY]], implicit-def $nzcv
+ ; CHECK-NEXT: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv
; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
@@ -238,7 +238,7 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK-NEXT: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
- ; CHECK-NEXT: FCMPSri [[COPY]], implicit-def $nzcv
+ ; CHECK-NEXT: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv
; CHECK-NEXT: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[FMOVS0_]], 1, implicit $nzcv
; CHECK-NEXT: $s0 = COPY [[FCSELSrrr]]
; CHECK-NEXT: RET_ReallyLR implicit $s0
@@ -269,7 +269,7 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK-NEXT: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
- ; CHECK-NEXT: FCMPDri [[COPY]], implicit-def $nzcv
+ ; CHECK-NEXT: nofpexcept FCMPDri [[COPY]], implicit-def $nzcv
; CHECK-NEXT: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[FMOVD0_]], [[COPY1]], 0, implicit $nzcv
; CHECK-NEXT: $d0 = COPY [[FCSELDrrr]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
@@ -300,7 +300,7 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK-NEXT: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
- ; CHECK-NEXT: FCMPDri [[COPY]], implicit-def $nzcv
+ ; CHECK-NEXT: nofpexcept FCMPDri [[COPY]], implicit-def $nzcv
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv
; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
@@ -337,7 +337,7 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK-NEXT: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
- ; CHECK-NEXT: FCMPDri [[COPY]], implicit-def $nzcv
+ ; CHECK-NEXT: nofpexcept FCMPDri [[COPY]], implicit-def $nzcv
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv
; CHECK-NEXT: [[CSINCWr1:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[CSINCWr]], [[CSINCWr1]]
@@ -374,7 +374,7 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK-NEXT: [[FMOVD0_:%[0-9]+]]:fpr64 = FMOVD0
- ; CHECK-NEXT: FCMPDri [[COPY]], implicit-def $nzcv
+ ; CHECK-NEXT: nofpexcept FCMPDri [[COPY]], implicit-def $nzcv
; CHECK-NEXT: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[COPY1]], [[FMOVD0_]], 1, implicit $nzcv
; CHECK-NEXT: $d0 = COPY [[FCSELDrrr]]
; CHECK-NEXT: RET_ReallyLR implicit $d0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/fold-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/fold-select.mir
index f60be78715374..363d3042a01cc 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/fold-select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/fold-select.mir
@@ -53,7 +53,7 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
- ; CHECK-NEXT: FCMPSri [[COPY1]], implicit-def $nzcv
+ ; CHECK-NEXT: nofpexcept FCMPSri [[COPY1]], implicit-def $nzcv
; CHECK-NEXT: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[COPY2]], [[COPY]], 0, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSELWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir b/llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir
index 3745c2119b524..fb9d6e3e5fd16 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir
@@ -31,7 +31,7 @@ body: |
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[CSELWr]], %bb.1, %8, %bb.2
- ; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[COPY]]
+ ; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[COPY]]
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[FCVTHSr]], %subreg.hsub
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: STRHHui [[PHI]], [[DEF1]], 0 :: (store (s16) into `half* undef`)
@@ -92,7 +92,7 @@ body: |
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI:%[0-9]+]]:fpr16 = PHI %7, %bb.2, [[COPY2]], %bb.1
- ; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[COPY]]
+ ; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[COPY]]
; CHECK-NEXT: STRHui [[PHI]], [[DEF1]], 0 :: (store (s16) into `half* undef`)
; CHECK-NEXT: B %bb.2
bb.0:
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir
index e56eb581ac601..24e42da55458c 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir
@@ -848,7 +848,7 @@ body: |
; CHECK-LABEL: name: fadd_s32_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
- ; CHECK: [[FADDSrr:%[0-9]+]]:fpr32 = FADDSrr [[COPY]], [[COPY1]]
+ ; CHECK: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr [[COPY]], [[COPY1]]
; CHECK: $s0 = COPY [[FADDSrr]]
%0(s32) = COPY $s0
%1(s32) = COPY $s1
@@ -873,7 +873,7 @@ body: |
; CHECK-LABEL: name: fadd_s64_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
- ; CHECK: [[FADDDrr:%[0-9]+]]:fpr64 = FADDDrr [[COPY]], [[COPY1]]
+ ; CHECK: [[FADDDrr:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[COPY]], [[COPY1]]
; CHECK: $d0 = COPY [[FADDDrr]]
%0(s64) = COPY $d0
%1(s64) = COPY $d1
@@ -898,7 +898,7 @@ body: |
; CHECK-LABEL: name: fsub_s32_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
- ; CHECK: [[FSUBSrr:%[0-9]+]]:fpr32 = FSUBSrr [[COPY]], [[COPY1]]
+ ; CHECK: [[FSUBSrr:%[0-9]+]]:fpr32 = nofpexcept FSUBSrr [[COPY]], [[COPY1]]
; CHECK: $s0 = COPY [[FSUBSrr]]
%0(s32) = COPY $s0
%1(s32) = COPY $s1
@@ -923,7 +923,7 @@ body: |
; CHECK-LABEL: name: fsub_s64_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
- ; CHECK: [[FSUBDrr:%[0-9]+]]:fpr64 = FSUBDrr [[COPY]], [[COPY1]]
+ ; CHECK: [[FSUBDrr:%[0-9]+]]:fpr64 = nofpexcept FSUBDrr [[COPY]], [[COPY1]]
; CHECK: $d0 = COPY [[FSUBDrr]]
%0(s64) = COPY $d0
%1(s64) = COPY $d1
@@ -948,7 +948,7 @@ body: |
; CHECK-LABEL: name: fmul_s32_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
- ; CHECK: [[FMULSrr:%[0-9]+]]:fpr32 = FMULSrr [[COPY]], [[COPY1]]
+ ; CHECK: [[FMULSrr:%[0-9]+]]:fpr32 = nofpexcept FMULSrr [[COPY]], [[COPY1]]
; CHECK: $s0 = COPY [[FMULSrr]]
%0(s32) = COPY $s0
%1(s32) = COPY $s1
@@ -973,7 +973,7 @@ body: |
; CHECK-LABEL: name: fmul_s64_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
- ; CHECK: [[FMULDrr:%[0-9]+]]:fpr64 = FMULDrr [[COPY]], [[COPY1]]
+ ; CHECK: [[FMULDrr:%[0-9]+]]:fpr64 = nofpexcept FMULDrr [[COPY]], [[COPY1]]
; CHECK: $d0 = COPY [[FMULDrr]]
%0(s64) = COPY $d0
%1(s64) = COPY $d1
@@ -998,7 +998,7 @@ body: |
; CHECK-LABEL: name: fdiv_s32_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
- ; CHECK: [[FDIVSrr:%[0-9]+]]:fpr32 = FDIVSrr [[COPY]], [[COPY1]]
+ ; CHECK: [[FDIVSrr:%[0-9]+]]:fpr32 = nofpexcept FDIVSrr [[COPY]], [[COPY1]]
; CHECK: $s0 = COPY [[FDIVSrr]]
%0(s32) = COPY $s0
%1(s32) = COPY $s1
@@ -1023,7 +1023,7 @@ body: |
; CHECK-LABEL: name: fdiv_s64_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
- ; CHECK: [[FDIVDrr:%[0-9]+]]:fpr64 = FDIVDrr [[COPY]], [[COPY1]]
+ ; CHECK: [[FDIVDrr:%[0-9]+]]:fpr64 = nofpexcept FDIVDrr [[COPY]], [[COPY1]]
; CHECK: $d0 = COPY [[FDIVDrr]]
%0(s64) = COPY $d0
%1(s64) = COPY $d1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-ceil.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-ceil.mir
index 9bacb7c75b9b3..c0150ae9f73f7 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-ceil.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-ceil.mir
@@ -13,7 +13,7 @@ registers:
body: |
bb.0:
; CHECK-LABEL: name: ceil_float
- ; CHECK: %{{[0-9]+}}:fpr32 = FRINTPSr %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:fpr32 = nofpexcept FRINTPSr %{{[0-9]+}}
liveins: $s0
%0:fpr(s32) = COPY $s0
%1:fpr(s32) = G_FCEIL %0
@@ -31,7 +31,7 @@ registers:
body: |
bb.0:
; CHECK-LABEL: name: ceil_double
- ; CHECK: %{{[0-9]+}}:fpr64 = FRINTPDr %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FRINTPDr %{{[0-9]+}}
liveins: $d0
%0:fpr(s64) = COPY $d0
%1:fpr(s64) = G_FCEIL %0
@@ -49,7 +49,7 @@ registers:
body: |
bb.0:
; CHECK-LABEL: name: ceil_v2f32
- ; CHECK: %{{[0-9]+}}:fpr64 = FRINTPv2f32 %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FRINTPv2f32 %{{[0-9]+}}
liveins: $d0
%0:fpr(<2 x s32>) = COPY $d0
%1:fpr(<2 x s32>) = G_FCEIL %0
@@ -67,7 +67,7 @@ registers:
body: |
bb.0:
; CHECK-LABEL: name: ceil_v4f32
- ; CHECK: %{{[0-9]+}}:fpr128 = FRINTPv4f32 %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FRINTPv4f32 %{{[0-9]+}}
liveins: $q0
%0:fpr(<4 x s32>) = COPY $q0
%1:fpr(<4 x s32>) = G_FCEIL %0
@@ -85,7 +85,7 @@ registers:
body: |
bb.0:
; CHECK-LABEL: name: ceil_v2f64
- ; CHECK: %{{[0-9]+}}:fpr128 = FRINTPv2f64 %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FRINTPv2f64 %{{[0-9]+}}
liveins: $q0
%0:fpr(<2 x s64>) = COPY $q0
%1:fpr(<2 x s64>) = G_FCEIL %0
@@ -103,7 +103,7 @@ registers:
body: |
bb.0:
; CHECK-LABEL: name: ceil_v4f16
- ; CHECK: %{{[0-9]+}}:fpr64 = FRINTPv4f16 %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FRINTPv4f16 %{{[0-9]+}}
liveins: $d0
%0:fpr(<4 x s16>) = COPY $d0
%1:fpr(<4 x s16>) = G_FCEIL %0
@@ -121,7 +121,7 @@ registers:
body: |
bb.0:
; CHECK-LABEL: name: ceil_v8f16
- ; CHECK: %{{[0-9]+}}:fpr128 = FRINTPv8f16 %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FRINTPv8f16 %{{[0-9]+}}
liveins: $q0
%0:fpr(<8 x s16>) = COPY $q0
%1:fpr(<8 x s16>) = G_FCEIL %0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-faddp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-faddp.mir
index 770630851d1b2..167d9b1db4989 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-faddp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-faddp.mir
@@ -17,7 +17,7 @@ body: |
; CHECK-LABEL: name: f64_faddp
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FADDPv2i64p:%[0-9]+]]:fpr64 = FADDPv2i64p [[COPY]]
+ ; CHECK: [[FADDPv2i64p:%[0-9]+]]:fpr64 = nofpexcept FADDPv2i64p [[COPY]]
; CHECK: $d0 = COPY [[FADDPv2i64p]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(<2 x s64>) = COPY $q0
@@ -47,7 +47,7 @@ body: |
; CHECK-LABEL: name: f32_faddp
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FADDPv2i32p:%[0-9]+]]:fpr32 = FADDPv2i32p [[COPY]]
+ ; CHECK: [[FADDPv2i32p:%[0-9]+]]:fpr32 = nofpexcept FADDPv2i32p [[COPY]]
; CHECK: $s0 = COPY [[FADDPv2i32p]]
; CHECK: RET_ReallyLR implicit $s0
%0:fpr(<2 x s32>) = COPY $d0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-fcmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-fcmp.mir
index cde785a6a4465..dd7487df40dbb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-fcmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-fcmp.mir
@@ -17,7 +17,7 @@ body: |
; CHECK-LABEL: name: zero
; CHECK: liveins: $s0, $s1
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK: FCMPSri [[COPY]], implicit-def $nzcv
+ ; CHECK: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK: $s0 = COPY [[CSINCWr]]
; CHECK: RET_ReallyLR implicit $s0
@@ -44,7 +44,7 @@ body: |
; CHECK: liveins: $s0, $s1
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: [[FMOVSi:%[0-9]+]]:fpr32 = FMOVSi 112
- ; CHECK: FCMPSrr [[COPY]], [[FMOVSi]], implicit-def $nzcv
+ ; CHECK: nofpexcept FCMPSrr [[COPY]], [[FMOVSi]], implicit-def $nzcv
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK: $s0 = COPY [[CSINCWr]]
; CHECK: RET_ReallyLR implicit $s0
@@ -71,7 +71,7 @@ body: |
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[FMOVDi:%[0-9]+]]:fpr64 = FMOVDi 112
- ; CHECK: FCMPDrr [[COPY]], [[FMOVDi]], implicit-def $nzcv
+ ; CHECK: nofpexcept FCMPDrr [[COPY]], [[FMOVDi]], implicit-def $nzcv
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK: $s0 = COPY [[CSINCWr]]
; CHECK: RET_ReallyLR implicit $s0
@@ -97,7 +97,7 @@ body: |
; CHECK-LABEL: name: zero_s64
; CHECK: liveins: $d0, $d1, $s0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: FCMPDri [[COPY]], implicit-def $nzcv
+ ; CHECK: nofpexcept FCMPDri [[COPY]], implicit-def $nzcv
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK: $s0 = COPY [[CSINCWr]]
; CHECK: RET_ReallyLR implicit $s0
@@ -122,7 +122,7 @@ body: |
; CHECK-LABEL: name: zero_lhs
; CHECK: liveins: $s0, $s1
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK: FCMPSri [[COPY]], implicit-def $nzcv
+ ; CHECK: nofpexcept FCMPSri [[COPY]], implicit-def $nzcv
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
; CHECK: $s0 = COPY [[CSINCWr]]
; CHECK: RET_ReallyLR implicit $s0
@@ -148,7 +148,7 @@ body: |
; CHECK: liveins: $s0, $s1
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
- ; CHECK: FCMPSrr [[FMOVS0_]], [[COPY]], implicit-def $nzcv
+ ; CHECK: nofpexcept FCMPSrr [[FMOVS0_]], [[COPY]], implicit-def $nzcv
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv
; CHECK: $s0 = COPY [[CSINCWr]]
; CHECK: RET_ReallyLR implicit $s0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-floor.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-floor.mir
index 23b95cf844f8a..af2478393f3f2 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-floor.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-floor.mir
@@ -13,7 +13,7 @@ registers:
body: |
bb.0:
; CHECK-LABEL: name: floor_float
- ; CHECK: %{{[0-9]+}}:fpr32 = FRINTMSr %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:fpr32 = nofpexcept FRINTMSr %{{[0-9]+}}
liveins: $s0
%0:fpr(s32) = COPY $s0
%1:fpr(s32) = G_FFLOOR %0
@@ -31,7 +31,7 @@ registers:
body: |
bb.0:
; CHECK-LABEL: name: floor_double
- ; CHECK: %{{[0-9]+}}:fpr64 = FRINTMDr %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FRINTMDr %{{[0-9]+}}
liveins: $d0
%0:fpr(s64) = COPY $d0
%1:fpr(s64) = G_FFLOOR %0
@@ -49,7 +49,7 @@ registers:
body: |
bb.0:
; CHECK-LABEL: name: floor_v2f32
- ; CHECK: %{{[0-9]+}}:fpr64 = FRINTMv2f32 %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FRINTMv2f32 %{{[0-9]+}}
liveins: $d0
%0:fpr(<2 x s32>) = COPY $d0
%1:fpr(<2 x s32>) = G_FFLOOR %0
@@ -67,7 +67,7 @@ registers:
body: |
bb.0:
; CHECK-LABEL: name: floor_v4f32
- ; CHECK: %{{[0-9]+}}:fpr128 = FRINTMv4f32 %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FRINTMv4f32 %{{[0-9]+}}
liveins: $q0
%0:fpr(<4 x s32>) = COPY $q0
%1:fpr(<4 x s32>) = G_FFLOOR %0
@@ -85,7 +85,7 @@ registers:
body: |
bb.0:
; CHECK-LABEL: name: floor_v2f64
- ; CHECK: %{{[0-9]+}}:fpr128 = FRINTMv2f64 %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FRINTMv2f64 %{{[0-9]+}}
liveins: $q0
%0:fpr(<2 x s64>) = COPY $q0
%1:fpr(<2 x s64>) = G_FFLOOR %0
@@ -103,7 +103,7 @@ registers:
body: |
bb.0:
; CHECK-LABEL: name: floor_v4f16
- ; CHECK: %{{[0-9]+}}:fpr64 = FRINTMv4f16 %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FRINTMv4f16 %{{[0-9]+}}
liveins: $d0
%0:fpr(<4 x s16>) = COPY $d0
%1:fpr(<4 x s16>) = G_FFLOOR %0
@@ -121,7 +121,7 @@ registers:
body: |
bb.0:
; CHECK-LABEL: name: floor_v8f16
- ; CHECK: %{{[0-9]+}}:fpr128 = FRINTMv8f16 %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FRINTMv8f16 %{{[0-9]+}}
liveins: $q0
%0:fpr(<8 x s16>) = COPY $q0
%1:fpr(<8 x s16>) = G_FFLOOR %0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-fma.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-fma.mir
index adac2ec253a89..5bde8c398af05 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-fma.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-fma.mir
@@ -26,7 +26,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $w1
; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $w2
- ; CHECK: [[FMADDSrrr:%[0-9]+]]:fpr32 = FMADDSrrr [[COPY]], [[COPY1]], [[COPY2]]
+ ; CHECK: [[FMADDSrrr:%[0-9]+]]:fpr32 = nofpexcept FMADDSrrr [[COPY]], [[COPY1]], [[COPY2]]
; CHECK: $w0 = COPY [[FMADDSrrr]]
%0(s32) = COPY $w0
%1(s32) = COPY $w1
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-fmul-indexed.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-fmul-indexed.mir
index 3d0beffe26581..2aca52ed8a40e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-fmul-indexed.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-fmul-indexed.mir
@@ -23,7 +23,7 @@ body: |
; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load (<2 x s32>), align 4)
; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[LDRDui]], %subreg.dsub
- ; CHECK: [[FMULv2i32_indexed:%[0-9]+]]:fpr64 = FMULv2i32_indexed [[COPY]], [[INSERT_SUBREG]], 0
+ ; CHECK: [[FMULv2i32_indexed:%[0-9]+]]:fpr64 = nofpexcept FMULv2i32_indexed [[COPY]], [[INSERT_SUBREG]], 0
; CHECK: $d0 = COPY [[FMULv2i32_indexed]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(<2 x s32>) = COPY $d0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
index c859e42548629..a9afc61cb42a6 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir
@@ -16,7 +16,7 @@ body: |
; CHECK-LABEL: name: fptrunc_s16_s32_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[COPY]]
+ ; CHECK: [[FCVTHSr:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[COPY]]
; CHECK: $h0 = COPY [[FCVTHSr]]
%0(s32) = COPY $s0
%1(s16) = G_FPTRUNC %0
@@ -38,7 +38,7 @@ body: |
; CHECK-LABEL: name: fptrunc_s16_s64_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FCVTHDr:%[0-9]+]]:fpr16 = FCVTHDr [[COPY]]
+ ; CHECK: [[FCVTHDr:%[0-9]+]]:fpr16 = nofpexcept FCVTHDr [[COPY]]
; CHECK: $h0 = COPY [[FCVTHDr]]
%0(s64) = COPY $d0
%1(s16) = G_FPTRUNC %0
@@ -60,7 +60,7 @@ body: |
; CHECK-LABEL: name: fptrunc_s32_s64_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FCVTSDr:%[0-9]+]]:fpr32 = FCVTSDr [[COPY]]
+ ; CHECK: [[FCVTSDr:%[0-9]+]]:fpr32 = nofpexcept FCVTSDr [[COPY]]
; CHECK: $s0 = COPY [[FCVTSDr]]
%0(s64) = COPY $d0
%1(s32) = G_FPTRUNC %0
@@ -81,7 +81,7 @@ body: |
liveins: $d0
; CHECK-LABEL: name: fptrunc_v4s16_v4s32_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FCVTNv4i16_:%[0-9]+]]:fpr64 = FCVTNv4i16 [[COPY]]
+ ; CHECK: [[FCVTNv4i16_:%[0-9]+]]:fpr64 = nofpexcept FCVTNv4i16 [[COPY]]
; CHECK: $d0 = COPY [[FCVTNv4i16_]]
%0(<4 x s32>) = COPY $q0
%1(<4 x s16>) = G_FPTRUNC %0
@@ -102,7 +102,7 @@ body: |
liveins: $q0
; CHECK-LABEL: name: fptrunc_v2s32_v2s64_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = FCVTNv2i32 [[COPY]]
+ ; CHECK: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = nofpexcept FCVTNv2i32 [[COPY]]
; CHECK: $d0 = COPY [[FCVTNv2i32_]]
%0(<2 x s64>) = COPY $q0
%1(<2 x s32>) = G_FPTRUNC %0
@@ -124,7 +124,7 @@ body: |
; CHECK-LABEL: name: fpext_s32_s16_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
- ; CHECK: [[FCVTSHr:%[0-9]+]]:fpr32 = FCVTSHr [[COPY]]
+ ; CHECK: [[FCVTSHr:%[0-9]+]]:fpr32 = nofpexcept FCVTSHr [[COPY]]
; CHECK: $s0 = COPY [[FCVTSHr]]
%0(s16) = COPY $h0
%1(s32) = G_FPEXT %0
@@ -146,7 +146,7 @@ body: |
; CHECK-LABEL: name: fpext_s64_s16_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
- ; CHECK: [[FCVTDHr:%[0-9]+]]:fpr64 = FCVTDHr [[COPY]]
+ ; CHECK: [[FCVTDHr:%[0-9]+]]:fpr64 = nofpexcept FCVTDHr [[COPY]]
; CHECK: $d0 = COPY [[FCVTDHr]]
%0(s16) = COPY $h0
%1(s64) = G_FPEXT %0
@@ -168,7 +168,7 @@ body: |
; CHECK-LABEL: name: fpext_s64_s32_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK: [[FCVTDSr:%[0-9]+]]:fpr64 = FCVTDSr [[COPY]]
+ ; CHECK: [[FCVTDSr:%[0-9]+]]:fpr64 = nofpexcept FCVTDSr [[COPY]]
; CHECK: $d0 = COPY [[FCVTDSr]]
%0(s32) = COPY $s0
%1(s64) = G_FPEXT %0
@@ -189,7 +189,7 @@ body: |
liveins: $d0
; CHECK-LABEL: name: fpext_v4s32_v4s16_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FCVTLv4i16_:%[0-9]+]]:fpr128 = FCVTLv4i16 [[COPY]]
+ ; CHECK: [[FCVTLv4i16_:%[0-9]+]]:fpr128 = nofpexcept FCVTLv4i16 [[COPY]]
; CHECK: $q0 = COPY [[FCVTLv4i16_]]
%0(<4 x s16>) = COPY $d0
%1(<4 x s32>) = G_FPEXT %0
@@ -210,7 +210,7 @@ body: |
liveins: $d0
; CHECK-LABEL: name: fpext_v2s64_v2s32_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = FCVTLv2i32 [[COPY]]
+ ; CHECK: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = nofpexcept FCVTLv2i32 [[COPY]]
; CHECK: $q0 = COPY [[FCVTLv2i32_]]
%0(<2 x s32>) = COPY $d0
%1(<2 x s64>) = G_FPEXT %0
@@ -232,7 +232,7 @@ body: |
; CHECK-LABEL: name: sitofp_s32_s32_fpr_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
- ; CHECK: [[SCVTFUWSri:%[0-9]+]]:fpr32 = SCVTFUWSri [[COPY]]
+ ; CHECK: [[SCVTFUWSri:%[0-9]+]]:fpr32 = nofpexcept SCVTFUWSri [[COPY]]
; CHECK: $s0 = COPY [[SCVTFUWSri]]
%0(s32) = COPY $w0
%1(s32) = G_SITOFP %0
@@ -254,7 +254,7 @@ body: |
; CHECK-LABEL: name: sitofp_s32_s32_fpr_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK: [[SCVTFv1i32_:%[0-9]+]]:fpr32 = SCVTFv1i32 [[COPY]]
+ ; CHECK: [[SCVTFv1i32_:%[0-9]+]]:fpr32 = nofpexcept SCVTFv1i32 [[COPY]]
; CHECK: $s0 = COPY [[SCVTFv1i32_]]
%0(s32) = COPY $s0
%1(s32) = G_SITOFP %0
@@ -276,7 +276,7 @@ body: |
; CHECK-LABEL: name: uitofp_s32_s32_fpr_fpr
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK: [[UCVTFv1i32_:%[0-9]+]]:fpr32 = UCVTFv1i32 [[COPY]]
+ ; CHECK: [[UCVTFv1i32_:%[0-9]+]]:fpr32 = nofpexcept UCVTFv1i32 [[COPY]]
; CHECK: $s0 = COPY [[UCVTFv1i32_]]
%0(s32) = COPY $s0
%1(s32) = G_UITOFP %0
@@ -298,7 +298,7 @@ body: |
; CHECK-LABEL: name: sitofp_s32_s64_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
- ; CHECK: [[SCVTFUXSri:%[0-9]+]]:fpr32 = SCVTFUXSri [[COPY]]
+ ; CHECK: [[SCVTFUXSri:%[0-9]+]]:fpr32 = nofpexcept SCVTFUXSri [[COPY]]
; CHECK: $s0 = COPY [[SCVTFUXSri]]
%0(s64) = COPY $x0
%1(s32) = G_SITOFP %0
@@ -320,7 +320,7 @@ body: |
; CHECK-LABEL: name: sitofp_s64_s32_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
- ; CHECK: [[SCVTFUWDri:%[0-9]+]]:fpr64 = SCVTFUWDri [[COPY]]
+ ; CHECK: [[SCVTFUWDri:%[0-9]+]]:fpr64 = nofpexcept SCVTFUWDri [[COPY]]
; CHECK: $d0 = COPY [[SCVTFUWDri]]
%0(s32) = COPY $w0
%1(s64) = G_SITOFP %0
@@ -343,7 +343,7 @@ body: |
; CHECK-LABEL: name: sitofp_s64_s32_fpr_both
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
- ; CHECK: [[SCVTFUWDri:%[0-9]+]]:fpr64 = SCVTFUWDri [[COPY1]]
+ ; CHECK: [[SCVTFUWDri:%[0-9]+]]:fpr64 = nofpexcept SCVTFUWDri [[COPY1]]
; CHECK: $d0 = COPY [[SCVTFUWDri]]
%0(s32) = COPY $s0
%1(s64) = G_SITOFP %0
@@ -365,7 +365,7 @@ body: |
; CHECK-LABEL: name: sitofp_s64_s64_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
- ; CHECK: [[SCVTFUXDri:%[0-9]+]]:fpr64 = SCVTFUXDri [[COPY]]
+ ; CHECK: [[SCVTFUXDri:%[0-9]+]]:fpr64 = nofpexcept SCVTFUXDri [[COPY]]
; CHECK: $d0 = COPY [[SCVTFUXDri]]
%0(s64) = COPY $x0
%1(s64) = G_SITOFP %0
@@ -387,7 +387,7 @@ body: |
; CHECK-LABEL: name: uitofp_s32_s32_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
- ; CHECK: [[UCVTFUWSri:%[0-9]+]]:fpr32 = UCVTFUWSri [[COPY]]
+ ; CHECK: [[UCVTFUWSri:%[0-9]+]]:fpr32 = nofpexcept UCVTFUWSri [[COPY]]
; CHECK: $s0 = COPY [[UCVTFUWSri]]
%0(s32) = COPY $w0
%1(s32) = G_UITOFP %0
@@ -409,7 +409,7 @@ body: |
; CHECK-LABEL: name: uitofp_s32_s64_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
- ; CHECK: [[UCVTFUXSri:%[0-9]+]]:fpr32 = UCVTFUXSri [[COPY]]
+ ; CHECK: [[UCVTFUXSri:%[0-9]+]]:fpr32 = nofpexcept UCVTFUXSri [[COPY]]
; CHECK: $s0 = COPY [[UCVTFUXSri]]
%0(s64) = COPY $x0
%1(s32) = G_UITOFP %0
@@ -431,7 +431,7 @@ body: |
; CHECK-LABEL: name: uitofp_s64_s32_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
- ; CHECK: [[UCVTFUWDri:%[0-9]+]]:fpr64 = UCVTFUWDri [[COPY]]
+ ; CHECK: [[UCVTFUWDri:%[0-9]+]]:fpr64 = nofpexcept UCVTFUWDri [[COPY]]
; CHECK: $d0 = COPY [[UCVTFUWDri]]
%0(s32) = COPY $w0
%1(s64) = G_UITOFP %0
@@ -453,7 +453,7 @@ body: |
; CHECK-LABEL: name: uitofp_s64_s64_fpr
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
- ; CHECK: [[UCVTFUXDri:%[0-9]+]]:fpr64 = UCVTFUXDri [[COPY]]
+ ; CHECK: [[UCVTFUXDri:%[0-9]+]]:fpr64 = nofpexcept UCVTFUXDri [[COPY]]
; CHECK: $d0 = COPY [[UCVTFUXDri]]
%0(s64) = COPY $x0
%1(s64) = G_UITOFP %0
@@ -475,7 +475,7 @@ body: |
; CHECK-LABEL: name: fptosi_s32_s32_gpr
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK: [[FCVTZSUWSr:%[0-9]+]]:gpr32 = FCVTZSUWSr [[COPY]]
+ ; CHECK: [[FCVTZSUWSr:%[0-9]+]]:gpr32 = nofpexcept FCVTZSUWSr [[COPY]]
; CHECK: $w0 = COPY [[FCVTZSUWSr]]
%0(s32) = COPY $s0
%1(s32) = G_FPTOSI %0
@@ -497,7 +497,7 @@ body: |
; CHECK-LABEL: name: fptosi_s32_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FCVTZSUWDr:%[0-9]+]]:gpr32 = FCVTZSUWDr [[COPY]]
+ ; CHECK: [[FCVTZSUWDr:%[0-9]+]]:gpr32 = nofpexcept FCVTZSUWDr [[COPY]]
; CHECK: $w0 = COPY [[FCVTZSUWDr]]
%0(s64) = COPY $d0
%1(s32) = G_FPTOSI %0
@@ -519,7 +519,7 @@ body: |
; CHECK-LABEL: name: fptosi_s64_s32_gpr
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK: [[FCVTZSUXSr:%[0-9]+]]:gpr64 = FCVTZSUXSr [[COPY]]
+ ; CHECK: [[FCVTZSUXSr:%[0-9]+]]:gpr64 = nofpexcept FCVTZSUXSr [[COPY]]
; CHECK: $x0 = COPY [[FCVTZSUXSr]]
%0(s32) = COPY $s0
%1(s64) = G_FPTOSI %0
@@ -541,7 +541,7 @@ body: |
; CHECK-LABEL: name: fptosi_s64_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FCVTZSUXDr:%[0-9]+]]:gpr64 = FCVTZSUXDr [[COPY]]
+ ; CHECK: [[FCVTZSUXDr:%[0-9]+]]:gpr64 = nofpexcept FCVTZSUXDr [[COPY]]
; CHECK: $x0 = COPY [[FCVTZSUXDr]]
%0(s64) = COPY $d0
%1(s64) = G_FPTOSI %0
@@ -563,7 +563,7 @@ body: |
; CHECK-LABEL: name: fptoui_s32_s32_gpr
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK: [[FCVTZUUWSr:%[0-9]+]]:gpr32 = FCVTZUUWSr [[COPY]]
+ ; CHECK: [[FCVTZUUWSr:%[0-9]+]]:gpr32 = nofpexcept FCVTZUUWSr [[COPY]]
; CHECK: $w0 = COPY [[FCVTZUUWSr]]
%0(s32) = COPY $s0
%1(s32) = G_FPTOUI %0
@@ -585,7 +585,7 @@ body: |
; CHECK-LABEL: name: fptoui_s32_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FCVTZUUWDr:%[0-9]+]]:gpr32 = FCVTZUUWDr [[COPY]]
+ ; CHECK: [[FCVTZUUWDr:%[0-9]+]]:gpr32 = nofpexcept FCVTZUUWDr [[COPY]]
; CHECK: $w0 = COPY [[FCVTZUUWDr]]
%0(s64) = COPY $d0
%1(s32) = G_FPTOUI %0
@@ -607,7 +607,7 @@ body: |
; CHECK-LABEL: name: fptoui_s64_s32_gpr
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK: [[FCVTZUUXSr:%[0-9]+]]:gpr64 = FCVTZUUXSr [[COPY]]
+ ; CHECK: [[FCVTZUUXSr:%[0-9]+]]:gpr64 = nofpexcept FCVTZUUXSr [[COPY]]
; CHECK: $x0 = COPY [[FCVTZUUXSr]]
%0(s32) = COPY $s0
%1(s64) = G_FPTOUI %0
@@ -629,7 +629,7 @@ body: |
; CHECK-LABEL: name: fptoui_s64_s64_gpr
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FCVTZUUXDr:%[0-9]+]]:gpr64 = FCVTZUUXDr [[COPY]]
+ ; CHECK: [[FCVTZUUXDr:%[0-9]+]]:gpr64 = nofpexcept FCVTZUUXDr [[COPY]]
; CHECK: $x0 = COPY [[FCVTZUUXDr]]
%0(s64) = COPY $d0
%1(s64) = G_FPTOUI %0
@@ -648,7 +648,7 @@ body: |
; CHECK-LABEL: name: sitofp_v2s64_v2s32
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[SSHLLv2i32_shift:%[0-9]+]]:fpr128 = SSHLLv2i32_shift [[COPY]], 0
- ; CHECK: [[SCVTFv2f64_:%[0-9]+]]:fpr128 = SCVTFv2f64 [[SSHLLv2i32_shift]]
+ ; CHECK: [[SCVTFv2f64_:%[0-9]+]]:fpr128 = nofpexcept SCVTFv2f64 [[SSHLLv2i32_shift]]
; CHECK: $q0 = COPY [[SCVTFv2f64_]]
%0:fpr(<2 x s32>) = COPY $d0
%1:fpr(<2 x s64>) = G_SITOFP %0
@@ -667,7 +667,7 @@ body: |
; CHECK-LABEL: name: uitofp_v2s64_v2s32
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 0
- ; CHECK: [[UCVTFv2f64_:%[0-9]+]]:fpr128 = UCVTFv2f64 [[USHLLv2i32_shift]]
+ ; CHECK: [[UCVTFv2f64_:%[0-9]+]]:fpr128 = nofpexcept UCVTFv2f64 [[USHLLv2i32_shift]]
; CHECK: $q0 = COPY [[UCVTFv2f64_]]
%0:fpr(<2 x s32>) = COPY $d0
%1:fpr(<2 x s64>) = G_UITOFP %0
@@ -685,8 +685,8 @@ body: |
; CHECK-LABEL: name: sitofp_v2s32_v2s64
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[SCVTFv2f64_:%[0-9]+]]:fpr128 = SCVTFv2f64 [[COPY]]
- ; CHECK: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = FCVTNv2i32 [[SCVTFv2f64_]]
+ ; CHECK: [[SCVTFv2f64_:%[0-9]+]]:fpr128 = nofpexcept SCVTFv2f64 [[COPY]]
+ ; CHECK: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = nofpexcept FCVTNv2i32 [[SCVTFv2f64_]]
; CHECK: $d0 = COPY [[FCVTNv2i32_]]
%0:fpr(<2 x s64>) = COPY $q0
%1:fpr(<2 x s32>) = G_SITOFP %0
@@ -704,8 +704,8 @@ body: |
; CHECK-LABEL: name: uitofp_v2s32_v2s64
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[UCVTFv2f64_:%[0-9]+]]:fpr128 = UCVTFv2f64 [[COPY]]
- ; CHECK: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = FCVTNv2i32 [[UCVTFv2f64_]]
+ ; CHECK: [[UCVTFv2f64_:%[0-9]+]]:fpr128 = nofpexcept UCVTFv2f64 [[COPY]]
+ ; CHECK: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = nofpexcept FCVTNv2i32 [[UCVTFv2f64_]]
; CHECK: $d0 = COPY [[FCVTNv2i32_]]
%0:fpr(<2 x s64>) = COPY $q0
%1:fpr(<2 x s32>) = G_UITOFP %0
@@ -723,8 +723,8 @@ body: |
; CHECK-LABEL: name: fptosi_v2s64_v2s32
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = FCVTLv2i32 [[COPY]]
- ; CHECK: [[FCVTZSv2f64_:%[0-9]+]]:fpr128 = FCVTZSv2f64 [[FCVTLv2i32_]]
+ ; CHECK: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = nofpexcept FCVTLv2i32 [[COPY]]
+ ; CHECK: [[FCVTZSv2f64_:%[0-9]+]]:fpr128 = nofpexcept FCVTZSv2f64 [[FCVTLv2i32_]]
; CHECK: $q0 = COPY [[FCVTZSv2f64_]]
%0:fpr(<2 x s32>) = COPY $d0
%1:fpr(<2 x s64>) = G_FPTOSI %0
@@ -742,8 +742,8 @@ body: |
; CHECK-LABEL: name: fptoui_v2s64_v2s32
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = FCVTLv2i32 [[COPY]]
- ; CHECK: [[FCVTZUv2f64_:%[0-9]+]]:fpr128 = FCVTZUv2f64 [[FCVTLv2i32_]]
+ ; CHECK: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = nofpexcept FCVTLv2i32 [[COPY]]
+ ; CHECK: [[FCVTZUv2f64_:%[0-9]+]]:fpr128 = nofpexcept FCVTZUv2f64 [[FCVTLv2i32_]]
; CHECK: $q0 = COPY [[FCVTZUv2f64_]]
%0:fpr(<2 x s32>) = COPY $d0
%1:fpr(<2 x s64>) = G_FPTOUI %0
@@ -761,7 +761,7 @@ body: |
; CHECK-LABEL: name: fptosi_v2s32_v2s64
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FCVTZSv2f64_:%[0-9]+]]:fpr128 = FCVTZSv2f64 [[COPY]]
+ ; CHECK: [[FCVTZSv2f64_:%[0-9]+]]:fpr128 = nofpexcept FCVTZSv2f64 [[COPY]]
; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[FCVTZSv2f64_]]
; CHECK: $d0 = COPY [[XTNv2i32_]]
%0:fpr(<2 x s64>) = COPY $q0
@@ -780,7 +780,7 @@ body: |
; CHECK-LABEL: name: fptoui_v2s32_v2s64
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FCVTZUv2f64_:%[0-9]+]]:fpr128 = FCVTZUv2f64 [[COPY]]
+ ; CHECK: [[FCVTZUv2f64_:%[0-9]+]]:fpr128 = nofpexcept FCVTZUv2f64 [[COPY]]
; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[FCVTZUv2f64_]]
; CHECK: $d0 = COPY [[XTNv2i32_]]
%0:fpr(<2 x s64>) = COPY $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir
index 0b010ffcf61cb..19714d775c355 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-frint-nofp16.mir
@@ -17,10 +17,10 @@ body: |
; CHECK: liveins: $h0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
- ; CHECK-NEXT: [[FCVTSHr:%[0-9]+]]:fpr32 = FCVTSHr [[COPY]]
- ; CHECK-NEXT: [[FRINTXSr:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr]]
- ; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr]]
- ; CHECK-NEXT: $h0 = COPY [[FCVTHSr]]
+ ; CHECK-NEXT: %1:fpr32 = nofpexcept FCVTSHr [[COPY]]
+ ; CHECK-NEXT: %2:fpr32 = nofpexcept FRINTXSr %1
+ ; CHECK-NEXT: %3:fpr16 = nofpexcept FCVTHSr %2
+ ; CHECK-NEXT: $h0 = COPY %3
; CHECK-NEXT: RET_ReallyLR implicit $h0
%0:fpr(s16) = COPY $h0
%2:fpr(s32) = G_FPEXT %0(s16)
@@ -55,28 +55,28 @@ body: |
; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG]], 1
; CHECK-NEXT: [[DUPi16_1:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG1]], 2
; CHECK-NEXT: [[DUPi16_2:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG2]], 3
- ; CHECK-NEXT: [[FCVTSHr:%[0-9]+]]:fpr32 = FCVTSHr [[COPY1]]
- ; CHECK-NEXT: [[FRINTXSr:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr]]
- ; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr]]
- ; CHECK-NEXT: [[FCVTSHr1:%[0-9]+]]:fpr32 = FCVTSHr [[DUPi16_]]
- ; CHECK-NEXT: [[FRINTXSr1:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr1]]
- ; CHECK-NEXT: [[FCVTHSr1:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr1]]
- ; CHECK-NEXT: [[FCVTSHr2:%[0-9]+]]:fpr32 = FCVTSHr [[DUPi16_1]]
- ; CHECK-NEXT: [[FRINTXSr2:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr2]]
- ; CHECK-NEXT: [[FCVTHSr2:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr2]]
- ; CHECK-NEXT: [[FCVTSHr3:%[0-9]+]]:fpr32 = FCVTSHr [[DUPi16_2]]
- ; CHECK-NEXT: [[FRINTXSr3:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr3]]
- ; CHECK-NEXT: [[FCVTHSr3:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr3]]
+ ; CHECK-NEXT: %5:fpr32 = nofpexcept FCVTSHr [[COPY1]]
+ ; CHECK-NEXT: %6:fpr32 = nofpexcept FRINTXSr %5
+ ; CHECK-NEXT: %7:fpr16 = nofpexcept FCVTHSr %6
+ ; CHECK-NEXT: %8:fpr32 = nofpexcept FCVTSHr [[DUPi16_]]
+ ; CHECK-NEXT: %9:fpr32 = nofpexcept FRINTXSr %8
+ ; CHECK-NEXT: %10:fpr16 = nofpexcept FCVTHSr %9
+ ; CHECK-NEXT: %11:fpr32 = nofpexcept FCVTSHr [[DUPi16_1]]
+ ; CHECK-NEXT: %12:fpr32 = nofpexcept FRINTXSr %11
+ ; CHECK-NEXT: %13:fpr16 = nofpexcept FCVTHSr %12
+ ; CHECK-NEXT: %14:fpr32 = nofpexcept FCVTSHr [[DUPi16_2]]
+ ; CHECK-NEXT: %15:fpr32 = nofpexcept FRINTXSr %14
+ ; CHECK-NEXT: %16:fpr16 = nofpexcept FCVTHSr %15
; CHECK-NEXT: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF
- ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[FCVTHSr]], %subreg.hsub
+ ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], %7, %subreg.hsub
; CHECK-NEXT: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF
- ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], [[FCVTHSr1]], %subreg.hsub
+ ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], %10, %subreg.hsub
; CHECK-NEXT: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG3]], 1, [[INSERT_SUBREG4]], 0
; CHECK-NEXT: [[DEF5:%[0-9]+]]:fpr128 = IMPLICIT_DEF
- ; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], [[FCVTHSr2]], %subreg.hsub
+ ; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], %13, %subreg.hsub
; CHECK-NEXT: [[INSvi16lane1:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane]], 2, [[INSERT_SUBREG5]], 0
; CHECK-NEXT: [[DEF6:%[0-9]+]]:fpr128 = IMPLICIT_DEF
- ; CHECK-NEXT: [[INSERT_SUBREG6:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF6]], [[FCVTHSr3]], %subreg.hsub
+ ; CHECK-NEXT: [[INSERT_SUBREG6:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF6]], %16, %subreg.hsub
; CHECK-NEXT: [[INSvi16lane2:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane1]], 3, [[INSERT_SUBREG6]], 0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi16lane2]].dsub
; CHECK-NEXT: $d0 = COPY [[COPY2]]
@@ -123,52 +123,52 @@ body: |
; CHECK-NEXT: [[DUPi16_4:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 5
; CHECK-NEXT: [[DUPi16_5:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 6
; CHECK-NEXT: [[DUPi16_6:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 7
- ; CHECK-NEXT: [[FCVTSHr:%[0-9]+]]:fpr32 = FCVTSHr [[COPY1]]
- ; CHECK-NEXT: [[FRINTXSr:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr]]
- ; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr]]
- ; CHECK-NEXT: [[FCVTSHr1:%[0-9]+]]:fpr32 = FCVTSHr [[DUPi16_]]
- ; CHECK-NEXT: [[FRINTXSr1:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr1]]
- ; CHECK-NEXT: [[FCVTHSr1:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr1]]
- ; CHECK-NEXT: [[FCVTSHr2:%[0-9]+]]:fpr32 = FCVTSHr [[DUPi16_1]]
- ; CHECK-NEXT: [[FRINTXSr2:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr2]]
- ; CHECK-NEXT: [[FCVTHSr2:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr2]]
- ; CHECK-NEXT: [[FCVTSHr3:%[0-9]+]]:fpr32 = FCVTSHr [[DUPi16_2]]
- ; CHECK-NEXT: [[FRINTXSr3:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr3]]
- ; CHECK-NEXT: [[FCVTHSr3:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr3]]
- ; CHECK-NEXT: [[FCVTSHr4:%[0-9]+]]:fpr32 = FCVTSHr [[DUPi16_3]]
- ; CHECK-NEXT: [[FRINTXSr4:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr4]]
- ; CHECK-NEXT: [[FCVTHSr4:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr4]]
- ; CHECK-NEXT: [[FCVTSHr5:%[0-9]+]]:fpr32 = FCVTSHr [[DUPi16_4]]
- ; CHECK-NEXT: [[FRINTXSr5:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr5]]
- ; CHECK-NEXT: [[FCVTHSr5:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr5]]
- ; CHECK-NEXT: [[FCVTSHr6:%[0-9]+]]:fpr32 = FCVTSHr [[DUPi16_5]]
- ; CHECK-NEXT: [[FRINTXSr6:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr6]]
- ; CHECK-NEXT: [[FCVTHSr6:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr6]]
- ; CHECK-NEXT: [[FCVTSHr7:%[0-9]+]]:fpr32 = FCVTSHr [[DUPi16_6]]
- ; CHECK-NEXT: [[FRINTXSr7:%[0-9]+]]:fpr32 = FRINTXSr [[FCVTSHr7]]
- ; CHECK-NEXT: [[FCVTHSr7:%[0-9]+]]:fpr16 = FCVTHSr [[FRINTXSr7]]
+ ; CHECK-NEXT: %9:fpr32 = nofpexcept FCVTSHr [[COPY1]]
+ ; CHECK-NEXT: %10:fpr32 = nofpexcept FRINTXSr %9
+ ; CHECK-NEXT: %11:fpr16 = nofpexcept FCVTHSr %10
+ ; CHECK-NEXT: %12:fpr32 = nofpexcept FCVTSHr [[DUPi16_]]
+ ; CHECK-NEXT: %13:fpr32 = nofpexcept FRINTXSr %12
+ ; CHECK-NEXT: %14:fpr16 = nofpexcept FCVTHSr %13
+ ; CHECK-NEXT: %15:fpr32 = nofpexcept FCVTSHr [[DUPi16_1]]
+ ; CHECK-NEXT: %16:fpr32 = nofpexcept FRINTXSr %15
+ ; CHECK-NEXT: %17:fpr16 = nofpexcept FCVTHSr %16
+ ; CHECK-NEXT: %18:fpr32 = nofpexcept FCVTSHr [[DUPi16_2]]
+ ; CHECK-NEXT: %19:fpr32 = nofpexcept FRINTXSr %18
+ ; CHECK-NEXT: %20:fpr16 = nofpexcept FCVTHSr %19
+ ; CHECK-NEXT: %21:fpr32 = nofpexcept FCVTSHr [[DUPi16_3]]
+ ; CHECK-NEXT: %22:fpr32 = nofpexcept FRINTXSr %21
+ ; CHECK-NEXT: %23:fpr16 = nofpexcept FCVTHSr %22
+ ; CHECK-NEXT: %24:fpr32 = nofpexcept FCVTSHr [[DUPi16_4]]
+ ; CHECK-NEXT: %25:fpr32 = nofpexcept FRINTXSr %24
+ ; CHECK-NEXT: %26:fpr16 = nofpexcept FCVTHSr %25
+ ; CHECK-NEXT: %27:fpr32 = nofpexcept FCVTSHr [[DUPi16_5]]
+ ; CHECK-NEXT: %28:fpr32 = nofpexcept FRINTXSr %27
+ ; CHECK-NEXT: %29:fpr16 = nofpexcept FCVTHSr %28
+ ; CHECK-NEXT: %30:fpr32 = nofpexcept FCVTSHr [[DUPi16_6]]
+ ; CHECK-NEXT: %31:fpr32 = nofpexcept FRINTXSr %30
+ ; CHECK-NEXT: %32:fpr16 = nofpexcept FCVTHSr %31
; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
- ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[FCVTHSr]], %subreg.hsub
+ ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %11, %subreg.hsub
; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
- ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[FCVTHSr1]], %subreg.hsub
+ ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], %14, %subreg.hsub
; CHECK-NEXT: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0
; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
- ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[FCVTHSr2]], %subreg.hsub
+ ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], %17, %subreg.hsub
; CHECK-NEXT: [[INSvi16lane1:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane]], 2, [[INSERT_SUBREG2]], 0
; CHECK-NEXT: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF
- ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[FCVTHSr3]], %subreg.hsub
+ ; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], %20, %subreg.hsub
; CHECK-NEXT: [[INSvi16lane2:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane1]], 3, [[INSERT_SUBREG3]], 0
; CHECK-NEXT: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF
- ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], [[FCVTHSr4]], %subreg.hsub
+ ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], %23, %subreg.hsub
; CHECK-NEXT: [[INSvi16lane3:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane2]], 4, [[INSERT_SUBREG4]], 0
; CHECK-NEXT: [[DEF5:%[0-9]+]]:fpr128 = IMPLICIT_DEF
- ; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], [[FCVTHSr5]], %subreg.hsub
+ ; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], %26, %subreg.hsub
; CHECK-NEXT: [[INSvi16lane4:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane3]], 5, [[INSERT_SUBREG5]], 0
; CHECK-NEXT: [[DEF6:%[0-9]+]]:fpr128 = IMPLICIT_DEF
- ; CHECK-NEXT: [[INSERT_SUBREG6:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF6]], [[FCVTHSr6]], %subreg.hsub
+ ; CHECK-NEXT: [[INSERT_SUBREG6:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF6]], %29, %subreg.hsub
; CHECK-NEXT: [[INSvi16lane5:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane4]], 6, [[INSERT_SUBREG6]], 0
; CHECK-NEXT: [[DEF7:%[0-9]+]]:fpr128 = IMPLICIT_DEF
- ; CHECK-NEXT: [[INSERT_SUBREG7:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF7]], [[FCVTHSr7]], %subreg.hsub
+ ; CHECK-NEXT: [[INSERT_SUBREG7:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF7]], %32, %subreg.hsub
; CHECK-NEXT: [[INSvi16lane6:%[0-9]+]]:fpr128 = INSvi16lane [[INSvi16lane5]], 7, [[INSERT_SUBREG7]], 0
; CHECK-NEXT: $q0 = COPY [[INSvi16lane6]]
; CHECK-NEXT: RET_ReallyLR implicit $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-frint.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-frint.mir
index 0f3e4cbc6ebac..a0856baece9f6 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-frint.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-frint.mir
@@ -16,7 +16,7 @@ body: |
; CHECK-LABEL: name: test_f16.rint
; CHECK: liveins: $h0
; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
- ; CHECK: [[FRINTXHr:%[0-9]+]]:fpr16 = FRINTXHr [[COPY]]
+ ; CHECK: [[FRINTXHr:%[0-9]+]]:fpr16 = nofpexcept FRINTXHr [[COPY]]
; CHECK: $h0 = COPY [[FRINTXHr]]
; CHECK: RET_ReallyLR implicit $h0
%0:fpr(s16) = COPY $h0
@@ -39,7 +39,7 @@ body: |
; CHECK-LABEL: name: test_f32.rint
; CHECK: liveins: $s0
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK: [[FRINTXSr:%[0-9]+]]:fpr32 = FRINTXSr [[COPY]]
+ ; CHECK: [[FRINTXSr:%[0-9]+]]:fpr32 = nofpexcept FRINTXSr [[COPY]]
; CHECK: $s0 = COPY [[FRINTXSr]]
; CHECK: RET_ReallyLR implicit $s0
%0:fpr(s32) = COPY $s0
@@ -62,7 +62,7 @@ body: |
; CHECK-LABEL: name: test_f64.rint
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FRINTXDr:%[0-9]+]]:fpr64 = FRINTXDr [[COPY]]
+ ; CHECK: [[FRINTXDr:%[0-9]+]]:fpr64 = nofpexcept FRINTXDr [[COPY]]
; CHECK: $d0 = COPY [[FRINTXDr]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(s64) = COPY $d0
@@ -85,7 +85,7 @@ body: |
; CHECK-LABEL: name: test_v4f32.rint
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FRINTXv4f32_:%[0-9]+]]:fpr128 = FRINTXv4f32 [[COPY]]
+ ; CHECK: [[FRINTXv4f32_:%[0-9]+]]:fpr128 = nofpexcept FRINTXv4f32 [[COPY]]
; CHECK: $q0 = COPY [[FRINTXv4f32_]]
; CHECK: RET_ReallyLR implicit $q0
%0:fpr(<4 x s32>) = COPY $q0
@@ -108,7 +108,7 @@ body: |
; CHECK-LABEL: name: test_v2f64.rint
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FRINTXv2f64_:%[0-9]+]]:fpr128 = FRINTXv2f64 [[COPY]]
+ ; CHECK: [[FRINTXv2f64_:%[0-9]+]]:fpr128 = nofpexcept FRINTXv2f64 [[COPY]]
; CHECK: $q0 = COPY [[FRINTXv2f64_]]
; CHECK: RET_ReallyLR implicit $q0
%0:fpr(<2 x s64>) = COPY $q0
@@ -131,7 +131,7 @@ body: |
; CHECK-LABEL: name: test_v4f16.rint
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FRINTXv4f16_:%[0-9]+]]:fpr64 = FRINTXv4f16 [[COPY]]
+ ; CHECK: [[FRINTXv4f16_:%[0-9]+]]:fpr64 = nofpexcept FRINTXv4f16 [[COPY]]
; CHECK: $d0 = COPY [[FRINTXv4f16_]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(<4 x s16>) = COPY $d0
@@ -154,7 +154,7 @@ body: |
; CHECK-LABEL: name: test_v8f16.rint
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FRINTXv8f16_:%[0-9]+]]:fpr128 = FRINTXv8f16 [[COPY]]
+ ; CHECK: [[FRINTXv8f16_:%[0-9]+]]:fpr128 = nofpexcept FRINTXv8f16 [[COPY]]
; CHECK: $q0 = COPY [[FRINTXv8f16_]]
; CHECK: RET_ReallyLR implicit $q0
%0:fpr(<8 x s16>) = COPY $q0
@@ -177,7 +177,7 @@ body: |
; CHECK-LABEL: name: test_v2f32.rint
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FRINTXv2f32_:%[0-9]+]]:fpr64 = FRINTXv2f32 [[COPY]]
+ ; CHECK: [[FRINTXv2f32_:%[0-9]+]]:fpr64 = nofpexcept FRINTXv2f32 [[COPY]]
; CHECK: $d0 = COPY [[FRINTXv2f32_]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(<2 x s32>) = COPY $d0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir
index ce2615b994225..606c673cc2803 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir
@@ -72,7 +72,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
- ; CHECK: [[FADDDrr:%[0-9]+]]:fpr64 = FADDDrr [[COPY]], [[LDRDui]]
+ ; CHECK: [[FADDDrr:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[COPY]], [[LDRDui]]
; CHECK: $d0 = COPY [[FADDDrr]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(s64) = COPY $d0
@@ -97,7 +97,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
; CHECK: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
- ; CHECK: [[FADDSrr:%[0-9]+]]:fpr32 = FADDSrr [[COPY]], [[LDRSui]]
+ ; CHECK: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr [[COPY]], [[LDRSui]]
; CHECK: $s0 = COPY [[FADDSrr]]
; CHECK: RET_ReallyLR implicit $s0
%0:fpr(s32) = COPY $s0
@@ -122,7 +122,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0
; CHECK: [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0
- ; CHECK: [[FADDSrr:%[0-9]+]]:fpr32 = FADDSrr [[COPY]], [[LDRSui]]
+ ; CHECK: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr [[COPY]], [[LDRSui]]
; CHECK: $s0 = COPY [[FADDSrr]]
; CHECK: RET_ReallyLR implicit $s0
%0:fpr(s32) = COPY $s0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-round.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-round.mir
index 3745e4a942d19..140d189a3af1d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-round.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-round.mir
@@ -16,7 +16,7 @@ body: |
; CHECK-LABEL: name: test_f64.intrinsic_round
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FRINTADr:%[0-9]+]]:fpr64 = FRINTADr [[COPY]]
+ ; CHECK: [[FRINTADr:%[0-9]+]]:fpr64 = nofpexcept FRINTADr [[COPY]]
; CHECK: $d0 = COPY [[FRINTADr]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(s64) = COPY $d0
@@ -39,7 +39,7 @@ body: |
; CHECK-LABEL: name: test_f32.intrinsic_round
; CHECK: liveins: $s0
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK: [[FRINTASr:%[0-9]+]]:fpr32 = FRINTASr [[COPY]]
+ ; CHECK: [[FRINTASr:%[0-9]+]]:fpr32 = nofpexcept FRINTASr [[COPY]]
; CHECK: $s0 = COPY [[FRINTASr]]
; CHECK: RET_ReallyLR implicit $s0
%0:fpr(s32) = COPY $s0
@@ -64,7 +64,7 @@ body: |
; CHECK-LABEL: name: test_f16.intrinsic_round
; CHECK: liveins: $h0
; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
- ; CHECK: [[FRINTAHr:%[0-9]+]]:fpr16 = FRINTAHr [[COPY]]
+ ; CHECK: [[FRINTAHr:%[0-9]+]]:fpr16 = nofpexcept FRINTAHr [[COPY]]
; CHECK: $h0 = COPY [[FRINTAHr]]
; CHECK: RET_ReallyLR implicit $h0
%0:fpr(s16) = COPY $h0
@@ -89,7 +89,7 @@ body: |
; CHECK-LABEL: name: test_v4f16.intrinsic_round
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FRINTAv4f16_:%[0-9]+]]:fpr64 = FRINTAv4f16 [[COPY]]
+ ; CHECK: [[FRINTAv4f16_:%[0-9]+]]:fpr64 = nofpexcept FRINTAv4f16 [[COPY]]
; CHECK: $d0 = COPY [[FRINTAv4f16_]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(<4 x s16>) = COPY $d0
@@ -114,7 +114,7 @@ body: |
; CHECK-LABEL: name: test_v8f16.intrinsic_round
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FRINTAv8f16_:%[0-9]+]]:fpr128 = FRINTAv8f16 [[COPY]]
+ ; CHECK: [[FRINTAv8f16_:%[0-9]+]]:fpr128 = nofpexcept FRINTAv8f16 [[COPY]]
; CHECK: $q0 = COPY [[FRINTAv8f16_]]
; CHECK: RET_ReallyLR implicit $q0
%0:fpr(<8 x s16>) = COPY $q0
@@ -139,7 +139,7 @@ body: |
; CHECK-LABEL: name: test_v2f32.intrinsic_round
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FRINTAv2f32_:%[0-9]+]]:fpr64 = FRINTAv2f32 [[COPY]]
+ ; CHECK: [[FRINTAv2f32_:%[0-9]+]]:fpr64 = nofpexcept FRINTAv2f32 [[COPY]]
; CHECK: $d0 = COPY [[FRINTAv2f32_]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(<2 x s32>) = COPY $d0
@@ -164,7 +164,7 @@ body: |
; CHECK-LABEL: name: test_v4f32.intrinsic_round
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FRINTAv4f32_:%[0-9]+]]:fpr128 = FRINTAv4f32 [[COPY]]
+ ; CHECK: [[FRINTAv4f32_:%[0-9]+]]:fpr128 = nofpexcept FRINTAv4f32 [[COPY]]
; CHECK: $q0 = COPY [[FRINTAv4f32_]]
; CHECK: RET_ReallyLR implicit $q0
%0:fpr(<4 x s32>) = COPY $q0
@@ -189,7 +189,7 @@ body: |
; CHECK-LABEL: name: test_v2f64.intrinsic_round
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FRINTAv2f64_:%[0-9]+]]:fpr128 = FRINTAv2f64 [[COPY]]
+ ; CHECK: [[FRINTAv2f64_:%[0-9]+]]:fpr128 = nofpexcept FRINTAv2f64 [[COPY]]
; CHECK: $q0 = COPY [[FRINTAv2f64_]]
; CHECK: RET_ReallyLR implicit $q0
%0:fpr(<2 x s64>) = COPY $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-trunc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-trunc.mir
index dd9aa1873287a..b76f0b0bff2d3 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-trunc.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-trunc.mir
@@ -16,7 +16,7 @@ body: |
; CHECK-LABEL: name: test_f64.intrinsic_trunc
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FRINTZDr:%[0-9]+]]:fpr64 = FRINTZDr [[COPY]]
+ ; CHECK: [[FRINTZDr:%[0-9]+]]:fpr64 = nofpexcept FRINTZDr [[COPY]]
; CHECK: $d0 = COPY [[FRINTZDr]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(s64) = COPY $d0
@@ -39,7 +39,7 @@ body: |
; CHECK-LABEL: name: test_f32.intrinsic_trunc
; CHECK: liveins: $s0
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK: [[FRINTZSr:%[0-9]+]]:fpr32 = FRINTZSr [[COPY]]
+ ; CHECK: [[FRINTZSr:%[0-9]+]]:fpr32 = nofpexcept FRINTZSr [[COPY]]
; CHECK: $s0 = COPY [[FRINTZSr]]
; CHECK: RET_ReallyLR implicit $s0
%0:fpr(s32) = COPY $s0
@@ -64,7 +64,7 @@ body: |
; CHECK-LABEL: name: test_f16.intrinsic_trunc
; CHECK: liveins: $h0
; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
- ; CHECK: [[FRINTZHr:%[0-9]+]]:fpr16 = FRINTZHr [[COPY]]
+ ; CHECK: [[FRINTZHr:%[0-9]+]]:fpr16 = nofpexcept FRINTZHr [[COPY]]
; CHECK: $h0 = COPY [[FRINTZHr]]
; CHECK: RET_ReallyLR implicit $h0
%0:fpr(s16) = COPY $h0
@@ -89,7 +89,7 @@ body: |
; CHECK-LABEL: name: test_v4f16.intrinsic_trunc
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FRINTZv4f16_:%[0-9]+]]:fpr64 = FRINTZv4f16 [[COPY]]
+ ; CHECK: [[FRINTZv4f16_:%[0-9]+]]:fpr64 = nofpexcept FRINTZv4f16 [[COPY]]
; CHECK: $d0 = COPY [[FRINTZv4f16_]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(<4 x s16>) = COPY $d0
@@ -114,7 +114,7 @@ body: |
; CHECK-LABEL: name: test_v8f16.intrinsic_trunc
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FRINTZv8f16_:%[0-9]+]]:fpr128 = FRINTZv8f16 [[COPY]]
+ ; CHECK: [[FRINTZv8f16_:%[0-9]+]]:fpr128 = nofpexcept FRINTZv8f16 [[COPY]]
; CHECK: $q0 = COPY [[FRINTZv8f16_]]
; CHECK: RET_ReallyLR implicit $q0
%0:fpr(<8 x s16>) = COPY $q0
@@ -139,7 +139,7 @@ body: |
; CHECK-LABEL: name: test_v2f32.intrinsic_trunc
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FRINTZv2f32_:%[0-9]+]]:fpr64 = FRINTZv2f32 [[COPY]]
+ ; CHECK: [[FRINTZv2f32_:%[0-9]+]]:fpr64 = nofpexcept FRINTZv2f32 [[COPY]]
; CHECK: $d0 = COPY [[FRINTZv2f32_]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(<2 x s32>) = COPY $d0
@@ -164,7 +164,7 @@ body: |
; CHECK-LABEL: name: test_v4f32.intrinsic_trunc
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FRINTZv4f32_:%[0-9]+]]:fpr128 = FRINTZv4f32 [[COPY]]
+ ; CHECK: [[FRINTZv4f32_:%[0-9]+]]:fpr128 = nofpexcept FRINTZv4f32 [[COPY]]
; CHECK: $q0 = COPY [[FRINTZv4f32_]]
; CHECK: RET_ReallyLR implicit $q0
%0:fpr(<4 x s32>) = COPY $q0
@@ -189,7 +189,7 @@ body: |
; CHECK-LABEL: name: test_v2f64.intrinsic_trunc
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FRINTZv2f64_:%[0-9]+]]:fpr128 = FRINTZv2f64 [[COPY]]
+ ; CHECK: [[FRINTZv2f64_:%[0-9]+]]:fpr128 = nofpexcept FRINTZv2f64 [[COPY]]
; CHECK: $q0 = COPY [[FRINTZv2f64_]]
; CHECK: RET_ReallyLR implicit $q0
%0:fpr(<2 x s64>) = COPY $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-nearbyint.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-nearbyint.mir
index 546be708db8fb..864d2e8fdcba8 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-nearbyint.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-nearbyint.mir
@@ -16,7 +16,7 @@ body: |
; CHECK-LABEL: name: test_v4f16.nearbyint
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FRINTIv4f16_:%[0-9]+]]:fpr64 = FRINTIv4f16 [[COPY]]
+ ; CHECK: [[FRINTIv4f16_:%[0-9]+]]:fpr64 = nofpexcept FRINTIv4f16 [[COPY]]
; CHECK: $d0 = COPY [[FRINTIv4f16_]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(<4 x s16>) = COPY $d0
@@ -39,7 +39,7 @@ body: |
; CHECK-LABEL: name: test_v8f16.nearbyint
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FRINTIv8f16_:%[0-9]+]]:fpr128 = FRINTIv8f16 [[COPY]]
+ ; CHECK: [[FRINTIv8f16_:%[0-9]+]]:fpr128 = nofpexcept FRINTIv8f16 [[COPY]]
; CHECK: $q0 = COPY [[FRINTIv8f16_]]
; CHECK: RET_ReallyLR implicit $q0
%0:fpr(<8 x s16>) = COPY $q0
@@ -62,7 +62,7 @@ body: |
; CHECK-LABEL: name: test_v2f32.nearbyint
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FRINTIv2f32_:%[0-9]+]]:fpr64 = FRINTIv2f32 [[COPY]]
+ ; CHECK: [[FRINTIv2f32_:%[0-9]+]]:fpr64 = nofpexcept FRINTIv2f32 [[COPY]]
; CHECK: $d0 = COPY [[FRINTIv2f32_]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(<2 x s32>) = COPY $d0
@@ -85,7 +85,7 @@ body: |
; CHECK-LABEL: name: test_v2f64.nearbyint
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FRINTIv2f64_:%[0-9]+]]:fpr128 = FRINTIv2f64 [[COPY]]
+ ; CHECK: [[FRINTIv2f64_:%[0-9]+]]:fpr128 = nofpexcept FRINTIv2f64 [[COPY]]
; CHECK: $q0 = COPY [[FRINTIv2f64_]]
; CHECK: RET_ReallyLR implicit $q0
%0:fpr(<2 x s64>) = COPY $q0
@@ -108,7 +108,7 @@ body: |
; CHECK-LABEL: name: test_f32.nearbyint
; CHECK: liveins: $s0
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK: [[FRINTISr:%[0-9]+]]:fpr32 = FRINTISr [[COPY]]
+ ; CHECK: [[FRINTISr:%[0-9]+]]:fpr32 = nofpexcept FRINTISr [[COPY]]
; CHECK: $s0 = COPY [[FRINTISr]]
; CHECK: RET_ReallyLR implicit $s0
%0:fpr(s32) = COPY $s0
@@ -131,7 +131,7 @@ body: |
; CHECK-LABEL: name: test_f64.nearbyint
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FRINTIDr:%[0-9]+]]:fpr64 = FRINTIDr [[COPY]]
+ ; CHECK: [[FRINTIDr:%[0-9]+]]:fpr64 = nofpexcept FRINTIDr [[COPY]]
; CHECK: $d0 = COPY [[FRINTIDr]]
; CHECK: RET_ReallyLR implicit $d0
%0:fpr(s64) = COPY $d0
@@ -154,7 +154,7 @@ body: |
; CHECK-LABEL: name: test_f16.nearbyint
; CHECK: liveins: $h0
; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
- ; CHECK: [[FRINTIHr:%[0-9]+]]:fpr16 = FRINTIHr [[COPY]]
+ ; CHECK: [[FRINTIHr:%[0-9]+]]:fpr16 = nofpexcept FRINTIHr [[COPY]]
; CHECK: $h0 = COPY [[FRINTIHr]]
; CHECK: RET_ReallyLR implicit $h0
%0:fpr(s16) = COPY $h0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vector-fcmp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vector-fcmp.mir
index f1ccc14e223f2..0b0c3ed763abc 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vector-fcmp.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vector-fcmp.mir
@@ -12,7 +12,7 @@ body: |
; CHECK-LABEL: name: fcmeq
; CHECK: %lhs:fpr128 = COPY $q0
; CHECK: %rhs:fpr128 = COPY $q1
- ; CHECK: %fcmp:fpr128 = FCMEQv2f64 %lhs, %rhs
+ ; CHECK: %fcmp:fpr128 = nofpexcept FCMEQv2f64 %lhs, %rhs
; CHECK: $q0 = COPY %fcmp
; CHECK: RET_ReallyLR implicit $q0
%lhs:fpr(<2 x s64>) = COPY $q0
@@ -32,7 +32,7 @@ body: |
; CHECK-LABEL: name: fcmge
; CHECK: %lhs:fpr128 = COPY $q0
; CHECK: %rhs:fpr128 = COPY $q1
- ; CHECK: %fcmp:fpr128 = FCMGEv2f64 %lhs, %rhs
+ ; CHECK: %fcmp:fpr128 = nofpexcept FCMGEv2f64 %lhs, %rhs
; CHECK: $q0 = COPY %fcmp
; CHECK: RET_ReallyLR implicit $q0
%lhs:fpr(<2 x s64>) = COPY $q0
@@ -52,7 +52,7 @@ body: |
; CHECK-LABEL: name: fcmgt
; CHECK: %lhs:fpr128 = COPY $q0
; CHECK: %rhs:fpr128 = COPY $q1
- ; CHECK: %fcmp:fpr128 = FCMGTv2f64 %lhs, %rhs
+ ; CHECK: %fcmp:fpr128 = nofpexcept FCMGTv2f64 %lhs, %rhs
; CHECK: $q0 = COPY %fcmp
; CHECK: RET_ReallyLR implicit $q0
%lhs:fpr(<2 x s64>) = COPY $q0
@@ -71,7 +71,7 @@ body: |
bb.0:
; CHECK-LABEL: name: fcmeqz
; CHECK: %lhs:fpr128 = COPY $q0
- ; CHECK: %fcmp:fpr128 = FCMEQv2i64rz %lhs
+ ; CHECK: %fcmp:fpr128 = nofpexcept FCMEQv2i64rz %lhs
; CHECK: $q0 = COPY %fcmp
; CHECK: RET_ReallyLR implicit $q0
%lhs:fpr(<2 x s64>) = COPY $q0
@@ -91,7 +91,7 @@ body: |
bb.0:
; CHECK-LABEL: name: fcmgez
; CHECK: %lhs:fpr128 = COPY $q0
- ; CHECK: %fcmp:fpr128 = FCMGEv2i64rz %lhs
+ ; CHECK: %fcmp:fpr128 = nofpexcept FCMGEv2i64rz %lhs
; CHECK: $q0 = COPY %fcmp
; CHECK: RET_ReallyLR implicit $q0
%lhs:fpr(<2 x s64>) = COPY $q0
@@ -111,7 +111,7 @@ body: |
bb.0:
; CHECK-LABEL: name: fcmgtz
; CHECK: %lhs:fpr128 = COPY $q0
- ; CHECK: %fcmp:fpr128 = FCMGTv2i64rz %lhs
+ ; CHECK: %fcmp:fpr128 = nofpexcept FCMGTv2i64rz %lhs
; CHECK: $q0 = COPY %fcmp
; CHECK: RET_ReallyLR implicit $q0
%lhs:fpr(<2 x s64>) = COPY $q0
@@ -131,7 +131,7 @@ body: |
bb.0:
; CHECK-LABEL: name: fcmlez
; CHECK: %lhs:fpr128 = COPY $q0
- ; CHECK: %fcmp:fpr128 = FCMLEv2i64rz %lhs
+ ; CHECK: %fcmp:fpr128 = nofpexcept FCMLEv2i64rz %lhs
; CHECK: $q0 = COPY %fcmp
; CHECK: RET_ReallyLR implicit $q0
%lhs:fpr(<2 x s64>) = COPY $q0
@@ -151,7 +151,7 @@ body: |
bb.0:
; CHECK-LABEL: name: fcmltz
; CHECK: %lhs:fpr128 = COPY $q0
- ; CHECK: %fcmp:fpr128 = FCMLTv2i64rz %lhs
+ ; CHECK: %fcmp:fpr128 = nofpexcept FCMLTv2i64rz %lhs
; CHECK: $q0 = COPY %fcmp
; CHECK: RET_ReallyLR implicit $q0
%lhs:fpr(<2 x s64>) = COPY $q0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-sqrt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-sqrt.mir
index 250fc213f830e..13ce9f9966b42 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-sqrt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-sqrt.mir
@@ -13,7 +13,7 @@ registers:
body: |
bb.0:
; CHECK-LABEL: name: sqrt_float
- ; CHECK: %{{[0-9]+}}:fpr32 = FSQRTSr %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:fpr32 = nofpexcept FSQRTSr %{{[0-9]+}}
liveins: $s0
%0:fpr(s32) = COPY $s0
%1:fpr(s32) = G_FSQRT %0
@@ -31,7 +31,7 @@ registers:
body: |
bb.0:
; CHECK-LABEL: name: sqrt_double
- ; CHECK: %{{[0-9]+}}:fpr64 = FSQRTDr %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FSQRTDr %{{[0-9]+}}
liveins: $d0
%0:fpr(s64) = COPY $d0
%1:fpr(s64) = G_FSQRT %0
@@ -49,7 +49,7 @@ registers:
body: |
bb.0:
; CHECK-LABEL: name: sqrt_v2f32
- ; CHECK: %{{[0-9]+}}:fpr64 = FSQRTv2f32 %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FSQRTv2f32 %{{[0-9]+}}
liveins: $d0
%0:fpr(<2 x s32>) = COPY $d0
%1:fpr(<2 x s32>) = G_FSQRT %0
@@ -67,7 +67,7 @@ registers:
body: |
bb.0:
; CHECK-LABEL: name: sqrt_v4f32
- ; CHECK: %{{[0-9]+}}:fpr128 = FSQRTv4f32 %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FSQRTv4f32 %{{[0-9]+}}
liveins: $q0
%0:fpr(<4 x s32>) = COPY $q0
%1:fpr(<4 x s32>) = G_FSQRT %0
@@ -85,7 +85,7 @@ registers:
body: |
bb.0:
; CHECK-LABEL: name: sqrt_v2f64
- ; CHECK: %{{[0-9]+}}:fpr128 = FSQRTv2f64 %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FSQRTv2f64 %{{[0-9]+}}
liveins: $q0
%0:fpr(<2 x s64>) = COPY $q0
%1:fpr(<2 x s64>) = G_FSQRT %0
@@ -103,7 +103,7 @@ registers:
body: |
bb.0:
; CHECK-LABEL: name: sqrt_v4f16
- ; CHECK: %{{[0-9]+}}:fpr64 = FSQRTv4f16 %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:fpr64 = nofpexcept FSQRTv4f16 %{{[0-9]+}}
liveins: $d0
%0:fpr(<4 x s16>) = COPY $d0
%1:fpr(<4 x s16>) = G_FSQRT %0
@@ -121,7 +121,7 @@ registers:
body: |
bb.0:
; CHECK-LABEL: name: sqrt_v8f16
- ; CHECK: %{{[0-9]+}}:fpr128 = FSQRTv8f16 %{{[0-9]+}}
+ ; CHECK: %{{[0-9]+}}:fpr128 = nofpexcept FSQRTv8f16 %{{[0-9]+}}
liveins: $q0
%0:fpr(<8 x s16>) = COPY $q0
%1:fpr(<8 x s16>) = G_FSQRT %0
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-static.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-static.mir
index dff2f093a9a4b..268256b0f2ea1 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-static.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-static.mir
@@ -182,12 +182,12 @@ registers:
- { id: 7, class: gpr }
# CHECK: body:
-# CHECK: FCMPSrr %0, %0, implicit-def $nzcv
+# CHECK: nofpexcept FCMPSrr %0, %0, implicit-def $nzcv
# CHECK: [[TST_MI:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv
# CHECK: [[TST_GT:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
# CHECK: %1:gpr32 = ORRWrr [[TST_MI]], [[TST_GT]]
-# CHECK: FCMPDrr %2, %2, implicit-def $nzcv
+# CHECK: nofpexcept FCMPDrr %2, %2, implicit-def $nzcv
# CHECK: %3:gpr32 = CSINCWr $wzr, $wzr, 4, implicit $nzcv
body: |
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
index 9d044d18b8c24..93d799f12c907 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-with-no-legality-check.mir
@@ -470,7 +470,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK: [[FNMADDSrrr:%[0-9]+]]:fpr32 = FNMADDSrrr [[COPY1]], [[COPY2]], [[COPY]]
+ ; CHECK: [[FNMADDSrrr:%[0-9]+]]:fpr32 = nofpexcept FNMADDSrrr [[COPY1]], [[COPY2]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FNMADDSrrr]]
%5:fpr(s32) = COPY $s2
%4:fpr(s32) = COPY $s1
@@ -507,7 +507,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FNMADDDrrr:%[0-9]+]]:fpr64 = FNMADDDrrr [[COPY1]], [[COPY2]], [[COPY]]
+ ; CHECK: [[FNMADDDrrr:%[0-9]+]]:fpr64 = nofpexcept FNMADDDrrr [[COPY1]], [[COPY2]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FNMADDDrrr]]
%5:fpr(s64) = COPY $d2
%4:fpr(s64) = COPY $d1
@@ -544,7 +544,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK: [[FNMADDSrrr:%[0-9]+]]:fpr32 = FNMADDSrrr [[COPY1]], [[COPY2]], [[COPY]]
+ ; CHECK: [[FNMADDSrrr:%[0-9]+]]:fpr32 = nofpexcept FNMADDSrrr [[COPY1]], [[COPY2]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FNMADDSrrr]]
%5:fpr(s32) = COPY $s2
%4:fpr(s32) = COPY $s1
@@ -581,7 +581,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FNMADDDrrr:%[0-9]+]]:fpr64 = FNMADDDrrr [[COPY1]], [[COPY2]], [[COPY]]
+ ; CHECK: [[FNMADDDrrr:%[0-9]+]]:fpr64 = nofpexcept FNMADDDrrr [[COPY1]], [[COPY2]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FNMADDDrrr]]
%5:fpr(s64) = COPY $d2
%4:fpr(s64) = COPY $d1
@@ -1013,7 +1013,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK: [[FMSUBSrrr:%[0-9]+]]:fpr32 = FMSUBSrrr [[COPY]], [[COPY2]], [[COPY1]]
+ ; CHECK: [[FMSUBSrrr:%[0-9]+]]:fpr32 = nofpexcept FMSUBSrrr [[COPY]], [[COPY2]], [[COPY1]]
; CHECK: $noreg = PATCHABLE_RET [[FMSUBSrrr]]
%4:fpr(s32) = COPY $s2
%3:fpr(s32) = COPY $s1
@@ -1048,7 +1048,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FMSUBDrrr:%[0-9]+]]:fpr64 = FMSUBDrrr [[COPY]], [[COPY2]], [[COPY1]]
+ ; CHECK: [[FMSUBDrrr:%[0-9]+]]:fpr64 = nofpexcept FMSUBDrrr [[COPY]], [[COPY2]], [[COPY1]]
; CHECK: $noreg = PATCHABLE_RET [[FMSUBDrrr]]
%4:fpr(s64) = COPY $d2
%3:fpr(s64) = COPY $d1
@@ -1083,7 +1083,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FMLSv2f32_:%[0-9]+]]:fpr64 = FMLSv2f32 [[COPY1]], [[COPY2]], [[COPY]]
+ ; CHECK: [[FMLSv2f32_:%[0-9]+]]:fpr64 = nofpexcept FMLSv2f32 [[COPY1]], [[COPY2]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FMLSv2f32_]]
%4:fpr(<2 x s32>) = COPY $d2
%3:fpr(<2 x s32>) = COPY $d1
@@ -1118,7 +1118,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FMLSv4f32_:%[0-9]+]]:fpr128 = FMLSv4f32 [[COPY1]], [[COPY2]], [[COPY]]
+ ; CHECK: [[FMLSv4f32_:%[0-9]+]]:fpr128 = nofpexcept FMLSv4f32 [[COPY1]], [[COPY2]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FMLSv4f32_]]
%4:fpr(<4 x s32>) = COPY $q2
%3:fpr(<4 x s32>) = COPY $q1
@@ -1153,7 +1153,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FMLSv2f64_:%[0-9]+]]:fpr128 = FMLSv2f64 [[COPY1]], [[COPY2]], [[COPY]]
+ ; CHECK: [[FMLSv2f64_:%[0-9]+]]:fpr128 = nofpexcept FMLSv2f64 [[COPY1]], [[COPY2]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FMLSv2f64_]]
%4:fpr(<2 x s64>) = COPY $q2
%3:fpr(<2 x s64>) = COPY $q1
@@ -1188,7 +1188,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK: [[FMSUBSrrr:%[0-9]+]]:fpr32 = FMSUBSrrr [[COPY2]], [[COPY]], [[COPY1]]
+ ; CHECK: [[FMSUBSrrr:%[0-9]+]]:fpr32 = nofpexcept FMSUBSrrr [[COPY2]], [[COPY]], [[COPY1]]
; CHECK: $noreg = PATCHABLE_RET [[FMSUBSrrr]]
%4:fpr(s32) = COPY $s2
%3:fpr(s32) = COPY $s1
@@ -1223,7 +1223,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FMSUBDrrr:%[0-9]+]]:fpr64 = FMSUBDrrr [[COPY2]], [[COPY]], [[COPY1]]
+ ; CHECK: [[FMSUBDrrr:%[0-9]+]]:fpr64 = nofpexcept FMSUBDrrr [[COPY2]], [[COPY]], [[COPY1]]
; CHECK: $noreg = PATCHABLE_RET [[FMSUBDrrr]]
%4:fpr(s64) = COPY $d2
%3:fpr(s64) = COPY $d1
@@ -1258,7 +1258,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FMLSv2f32_:%[0-9]+]]:fpr64 = FMLSv2f32 [[COPY1]], [[COPY2]], [[COPY]]
+ ; CHECK: [[FMLSv2f32_:%[0-9]+]]:fpr64 = nofpexcept FMLSv2f32 [[COPY1]], [[COPY2]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FMLSv2f32_]]
%4:fpr(<2 x s32>) = COPY $d2
%3:fpr(<2 x s32>) = COPY $d1
@@ -1293,7 +1293,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FMLSv4f32_:%[0-9]+]]:fpr128 = FMLSv4f32 [[COPY1]], [[COPY2]], [[COPY]]
+ ; CHECK: [[FMLSv4f32_:%[0-9]+]]:fpr128 = nofpexcept FMLSv4f32 [[COPY1]], [[COPY2]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FMLSv4f32_]]
%4:fpr(<4 x s32>) = COPY $q2
%3:fpr(<4 x s32>) = COPY $q1
@@ -1328,7 +1328,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FMLSv2f64_:%[0-9]+]]:fpr128 = FMLSv2f64 [[COPY1]], [[COPY2]], [[COPY]]
+ ; CHECK: [[FMLSv2f64_:%[0-9]+]]:fpr128 = nofpexcept FMLSv2f64 [[COPY1]], [[COPY2]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FMLSv2f64_]]
%4:fpr(<2 x s64>) = COPY $q2
%3:fpr(<2 x s64>) = COPY $q1
@@ -1363,7 +1363,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK: [[FNMSUBSrrr:%[0-9]+]]:fpr32 = FNMSUBSrrr [[COPY2]], [[COPY1]], [[COPY]]
+ ; CHECK: [[FNMSUBSrrr:%[0-9]+]]:fpr32 = nofpexcept FNMSUBSrrr [[COPY2]], [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FNMSUBSrrr]]
%4:fpr(s32) = COPY $s2
%3:fpr(s32) = COPY $s1
@@ -1398,7 +1398,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FNMSUBDrrr:%[0-9]+]]:fpr64 = FNMSUBDrrr [[COPY2]], [[COPY1]], [[COPY]]
+ ; CHECK: [[FNMSUBDrrr:%[0-9]+]]:fpr64 = nofpexcept FNMSUBDrrr [[COPY2]], [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FNMSUBDrrr]]
%4:fpr(s64) = COPY $d2
%3:fpr(s64) = COPY $d1
@@ -2423,7 +2423,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK: [[FNMADDSrrr:%[0-9]+]]:fpr32 = FNMADDSrrr [[COPY2]], [[COPY1]], [[COPY]]
+ ; CHECK: [[FNMADDSrrr:%[0-9]+]]:fpr32 = nofpexcept FNMADDSrrr [[COPY2]], [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FNMADDSrrr]]
%4:fpr(s32) = COPY $s2
%3:fpr(s32) = COPY $s1
@@ -2458,7 +2458,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FNMADDDrrr:%[0-9]+]]:fpr64 = FNMADDDrrr [[COPY2]], [[COPY1]], [[COPY]]
+ ; CHECK: [[FNMADDDrrr:%[0-9]+]]:fpr64 = nofpexcept FNMADDDrrr [[COPY2]], [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FNMADDDrrr]]
%4:fpr(s64) = COPY $d2
%3:fpr(s64) = COPY $d1
@@ -2490,7 +2490,7 @@ body: |
; CHECK: liveins: $s0, $s1
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s1
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
- ; CHECK: [[FNMULSrr:%[0-9]+]]:fpr32 = FNMULSrr [[COPY1]], [[COPY]]
+ ; CHECK: [[FNMULSrr:%[0-9]+]]:fpr32 = nofpexcept FNMULSrr [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FNMULSrr]]
%3:fpr(s32) = COPY $s1
%2:fpr(s32) = COPY $s0
@@ -2521,7 +2521,7 @@ body: |
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FNMULDrr:%[0-9]+]]:fpr64 = FNMULDrr [[COPY1]], [[COPY]]
+ ; CHECK: [[FNMULDrr:%[0-9]+]]:fpr64 = nofpexcept FNMULDrr [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FNMULDrr]]
%3:fpr(s64) = COPY $d1
%2:fpr(s64) = COPY $d0
@@ -2612,7 +2612,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FMLAv2f32_:%[0-9]+]]:fpr64 = FMLAv2f32 [[COPY]], [[COPY1]], [[COPY2]]
+ ; CHECK: [[FMLAv2f32_:%[0-9]+]]:fpr64 = nofpexcept FMLAv2f32 [[COPY]], [[COPY1]], [[COPY2]]
; CHECK: $noreg = PATCHABLE_RET [[FMLAv2f32_]]
%3:fpr(<2 x s32>) = COPY $d2
%2:fpr(<2 x s32>) = COPY $d1
@@ -2645,7 +2645,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FMLAv4f32_:%[0-9]+]]:fpr128 = FMLAv4f32 [[COPY]], [[COPY1]], [[COPY2]]
+ ; CHECK: [[FMLAv4f32_:%[0-9]+]]:fpr128 = nofpexcept FMLAv4f32 [[COPY]], [[COPY1]], [[COPY2]]
; CHECK: $noreg = PATCHABLE_RET [[FMLAv4f32_]]
%3:fpr(<4 x s32>) = COPY $q2
%2:fpr(<4 x s32>) = COPY $q1
@@ -2678,7 +2678,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FMLAv2f64_:%[0-9]+]]:fpr128 = FMLAv2f64 [[COPY]], [[COPY1]], [[COPY2]]
+ ; CHECK: [[FMLAv2f64_:%[0-9]+]]:fpr128 = nofpexcept FMLAv2f64 [[COPY]], [[COPY1]], [[COPY2]]
; CHECK: $noreg = PATCHABLE_RET [[FMLAv2f64_]]
%3:fpr(<2 x s64>) = COPY $q2
%2:fpr(<2 x s64>) = COPY $q1
@@ -2940,7 +2940,7 @@ body: |
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FADDv2f32_:%[0-9]+]]:fpr64 = FADDv2f32 [[COPY1]], [[COPY]]
+ ; CHECK: [[FADDv2f32_:%[0-9]+]]:fpr64 = nofpexcept FADDv2f32 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FADDv2f32_]]
%2:fpr(<2 x s32>) = COPY $d1
%1:fpr(<2 x s32>) = COPY $d0
@@ -2969,7 +2969,7 @@ body: |
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FADDv4f32_:%[0-9]+]]:fpr128 = FADDv4f32 [[COPY1]], [[COPY]]
+ ; CHECK: [[FADDv4f32_:%[0-9]+]]:fpr128 = nofpexcept FADDv4f32 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FADDv4f32_]]
%2:fpr(<4 x s32>) = COPY $q1
%1:fpr(<4 x s32>) = COPY $q0
@@ -2998,7 +2998,7 @@ body: |
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FADDv2f64_:%[0-9]+]]:fpr128 = FADDv2f64 [[COPY1]], [[COPY]]
+ ; CHECK: [[FADDv2f64_:%[0-9]+]]:fpr128 = nofpexcept FADDv2f64 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FADDv2f64_]]
%2:fpr(<2 x s64>) = COPY $q1
%1:fpr(<2 x s64>) = COPY $q0
@@ -3027,7 +3027,7 @@ body: |
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FDIVv2f32_:%[0-9]+]]:fpr64 = FDIVv2f32 [[COPY1]], [[COPY]]
+ ; CHECK: [[FDIVv2f32_:%[0-9]+]]:fpr64 = nofpexcept FDIVv2f32 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FDIVv2f32_]]
%2:fpr(<2 x s32>) = COPY $d1
%1:fpr(<2 x s32>) = COPY $d0
@@ -3056,7 +3056,7 @@ body: |
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FDIVv4f32_:%[0-9]+]]:fpr128 = FDIVv4f32 [[COPY1]], [[COPY]]
+ ; CHECK: [[FDIVv4f32_:%[0-9]+]]:fpr128 = nofpexcept FDIVv4f32 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FDIVv4f32_]]
%2:fpr(<4 x s32>) = COPY $q1
%1:fpr(<4 x s32>) = COPY $q0
@@ -3085,7 +3085,7 @@ body: |
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FDIVv2f64_:%[0-9]+]]:fpr128 = FDIVv2f64 [[COPY1]], [[COPY]]
+ ; CHECK: [[FDIVv2f64_:%[0-9]+]]:fpr128 = nofpexcept FDIVv2f64 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FDIVv2f64_]]
%2:fpr(<2 x s64>) = COPY $q1
%1:fpr(<2 x s64>) = COPY $q0
@@ -3114,7 +3114,7 @@ body: |
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FMULv2f32_:%[0-9]+]]:fpr64 = FMULv2f32 [[COPY1]], [[COPY]]
+ ; CHECK: [[FMULv2f32_:%[0-9]+]]:fpr64 = nofpexcept FMULv2f32 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FMULv2f32_]]
%2:fpr(<2 x s32>) = COPY $d1
%1:fpr(<2 x s32>) = COPY $d0
@@ -3143,7 +3143,7 @@ body: |
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FMULv4f32_:%[0-9]+]]:fpr128 = FMULv4f32 [[COPY1]], [[COPY]]
+ ; CHECK: [[FMULv4f32_:%[0-9]+]]:fpr128 = nofpexcept FMULv4f32 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FMULv4f32_]]
%2:fpr(<4 x s32>) = COPY $q1
%1:fpr(<4 x s32>) = COPY $q0
@@ -3172,7 +3172,7 @@ body: |
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FMULv2f64_:%[0-9]+]]:fpr128 = FMULv2f64 [[COPY1]], [[COPY]]
+ ; CHECK: [[FMULv2f64_:%[0-9]+]]:fpr128 = nofpexcept FMULv2f64 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FMULv2f64_]]
%2:fpr(<2 x s64>) = COPY $q1
%1:fpr(<2 x s64>) = COPY $q0
@@ -3201,7 +3201,7 @@ body: |
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FSUBv2f32_:%[0-9]+]]:fpr64 = FSUBv2f32 [[COPY1]], [[COPY]]
+ ; CHECK: [[FSUBv2f32_:%[0-9]+]]:fpr64 = nofpexcept FSUBv2f32 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FSUBv2f32_]]
%2:fpr(<2 x s32>) = COPY $d1
%1:fpr(<2 x s32>) = COPY $d0
@@ -3230,7 +3230,7 @@ body: |
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FSUBv4f32_:%[0-9]+]]:fpr128 = FSUBv4f32 [[COPY1]], [[COPY]]
+ ; CHECK: [[FSUBv4f32_:%[0-9]+]]:fpr128 = nofpexcept FSUBv4f32 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FSUBv4f32_]]
%2:fpr(<4 x s32>) = COPY $q1
%1:fpr(<4 x s32>) = COPY $q0
@@ -3259,7 +3259,7 @@ body: |
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FSUBv2f64_:%[0-9]+]]:fpr128 = FSUBv2f64 [[COPY1]], [[COPY]]
+ ; CHECK: [[FSUBv2f64_:%[0-9]+]]:fpr128 = nofpexcept FSUBv2f64 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FSUBv2f64_]]
%2:fpr(<2 x s64>) = COPY $q1
%1:fpr(<2 x s64>) = COPY $q0
@@ -3949,7 +3949,7 @@ body: |
; CHECK-LABEL: name: test_rule1592_id2383_at_idx97425
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = FCVTLv2i32 [[COPY]]
+ ; CHECK: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = nofpexcept FCVTLv2i32 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FCVTLv2i32_]]
%1:fpr(<2 x s32>) = COPY $d0
%0:fpr(<2 x s64>) = G_FPEXT %1(<2 x s32>)
@@ -3974,7 +3974,7 @@ body: |
; CHECK-LABEL: name: test_rule1593_id2385_at_idx97458
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FCVTLv4i16_:%[0-9]+]]:fpr128 = FCVTLv4i16 [[COPY]]
+ ; CHECK: [[FCVTLv4i16_:%[0-9]+]]:fpr128 = nofpexcept FCVTLv4i16 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FCVTLv4i16_]]
%1:fpr(<4 x s16>) = COPY $d0
%0:fpr(<4 x s32>) = G_FPEXT %1(<4 x s16>)
@@ -3999,7 +3999,7 @@ body: |
; CHECK-LABEL: name: test_rule1602_id587_at_idx97771
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FCVTZSv2f32_:%[0-9]+]]:fpr64 = FCVTZSv2f32 [[COPY]]
+ ; CHECK: [[FCVTZSv2f32_:%[0-9]+]]:fpr64 = nofpexcept FCVTZSv2f32 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FCVTZSv2f32_]]
%1:fpr(<2 x s32>) = COPY $d0
%0:fpr(<2 x s32>) = G_FPTOSI %1(<2 x s32>)
@@ -4024,7 +4024,7 @@ body: |
; CHECK-LABEL: name: test_rule1603_id588_at_idx97806
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FCVTZSv4f32_:%[0-9]+]]:fpr128 = FCVTZSv4f32 [[COPY]]
+ ; CHECK: [[FCVTZSv4f32_:%[0-9]+]]:fpr128 = nofpexcept FCVTZSv4f32 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FCVTZSv4f32_]]
%1:fpr(<4 x s32>) = COPY $q0
%0:fpr(<4 x s32>) = G_FPTOSI %1(<4 x s32>)
@@ -4049,7 +4049,7 @@ body: |
; CHECK-LABEL: name: test_rule1604_id589_at_idx97841
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FCVTZSv2f64_:%[0-9]+]]:fpr128 = FCVTZSv2f64 [[COPY]]
+ ; CHECK: [[FCVTZSv2f64_:%[0-9]+]]:fpr128 = nofpexcept FCVTZSv2f64 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FCVTZSv2f64_]]
%1:fpr(<2 x s64>) = COPY $q0
%0:fpr(<2 x s64>) = G_FPTOSI %1(<2 x s64>)
@@ -4074,7 +4074,7 @@ body: |
; CHECK-LABEL: name: test_rule1613_id592_at_idx98156
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[FCVTZUv2f32_:%[0-9]+]]:fpr64 = FCVTZUv2f32 [[COPY]]
+ ; CHECK: [[FCVTZUv2f32_:%[0-9]+]]:fpr64 = nofpexcept FCVTZUv2f32 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FCVTZUv2f32_]]
%1:fpr(<2 x s32>) = COPY $d0
%0:fpr(<2 x s32>) = G_FPTOUI %1(<2 x s32>)
@@ -4099,7 +4099,7 @@ body: |
; CHECK-LABEL: name: test_rule1614_id593_at_idx98191
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FCVTZUv4f32_:%[0-9]+]]:fpr128 = FCVTZUv4f32 [[COPY]]
+ ; CHECK: [[FCVTZUv4f32_:%[0-9]+]]:fpr128 = nofpexcept FCVTZUv4f32 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FCVTZUv4f32_]]
%1:fpr(<4 x s32>) = COPY $q0
%0:fpr(<4 x s32>) = G_FPTOUI %1(<4 x s32>)
@@ -4124,7 +4124,7 @@ body: |
; CHECK-LABEL: name: test_rule1615_id594_at_idx98226
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FCVTZUv2f64_:%[0-9]+]]:fpr128 = FCVTZUv2f64 [[COPY]]
+ ; CHECK: [[FCVTZUv2f64_:%[0-9]+]]:fpr128 = nofpexcept FCVTZUv2f64 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FCVTZUv2f64_]]
%1:fpr(<2 x s64>) = COPY $q0
%0:fpr(<2 x s64>) = G_FPTOUI %1(<2 x s64>)
@@ -4149,7 +4149,7 @@ body: |
; CHECK-LABEL: name: test_rule1619_id2389_at_idx98366
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = FCVTNv2i32 [[COPY]]
+ ; CHECK: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = nofpexcept FCVTNv2i32 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FCVTNv2i32_]]
%1:fpr(<2 x s64>) = COPY $q0
%0:fpr(<2 x s32>) = G_FPTRUNC %1(<2 x s64>)
@@ -4174,7 +4174,7 @@ body: |
; CHECK-LABEL: name: test_rule1620_id2390_at_idx98399
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[FCVTNv4i16_:%[0-9]+]]:fpr64 = FCVTNv4i16 [[COPY]]
+ ; CHECK: [[FCVTNv4i16_:%[0-9]+]]:fpr64 = nofpexcept FCVTNv4i16 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FCVTNv4i16_]]
%1:fpr(<4 x s32>) = COPY $q0
%0:fpr(<4 x s16>) = G_FPTRUNC %1(<4 x s32>)
@@ -4274,7 +4274,7 @@ body: |
; CHECK-LABEL: name: test_rule1632_id687_at_idx98847
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[SCVTFv2f32_:%[0-9]+]]:fpr64 = SCVTFv2f32 [[COPY]]
+ ; CHECK: [[SCVTFv2f32_:%[0-9]+]]:fpr64 = nofpexcept SCVTFv2f32 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[SCVTFv2f32_]]
%1:fpr(<2 x s32>) = COPY $d0
%0:fpr(<2 x s32>) = G_SITOFP %1(<2 x s32>)
@@ -4299,7 +4299,7 @@ body: |
; CHECK-LABEL: name: test_rule1633_id688_at_idx98882
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[SCVTFv4f32_:%[0-9]+]]:fpr128 = SCVTFv4f32 [[COPY]]
+ ; CHECK: [[SCVTFv4f32_:%[0-9]+]]:fpr128 = nofpexcept SCVTFv4f32 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[SCVTFv4f32_]]
%1:fpr(<4 x s32>) = COPY $q0
%0:fpr(<4 x s32>) = G_SITOFP %1(<4 x s32>)
@@ -4324,7 +4324,7 @@ body: |
; CHECK-LABEL: name: test_rule1634_id689_at_idx98917
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[SCVTFv2f64_:%[0-9]+]]:fpr128 = SCVTFv2f64 [[COPY]]
+ ; CHECK: [[SCVTFv2f64_:%[0-9]+]]:fpr128 = nofpexcept SCVTFv2f64 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[SCVTFv2f64_]]
%1:fpr(<2 x s64>) = COPY $q0
%0:fpr(<2 x s64>) = G_SITOFP %1(<2 x s64>)
@@ -4424,7 +4424,7 @@ body: |
; CHECK-LABEL: name: test_rule1647_id731_at_idx99386
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
- ; CHECK: [[UCVTFv2f32_:%[0-9]+]]:fpr64 = UCVTFv2f32 [[COPY]]
+ ; CHECK: [[UCVTFv2f32_:%[0-9]+]]:fpr64 = nofpexcept UCVTFv2f32 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[UCVTFv2f32_]]
%1:fpr(<2 x s32>) = COPY $d0
%0:fpr(<2 x s32>) = G_UITOFP %1(<2 x s32>)
@@ -4449,7 +4449,7 @@ body: |
; CHECK-LABEL: name: test_rule1648_id732_at_idx99421
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[UCVTFv4f32_:%[0-9]+]]:fpr128 = UCVTFv4f32 [[COPY]]
+ ; CHECK: [[UCVTFv4f32_:%[0-9]+]]:fpr128 = nofpexcept UCVTFv4f32 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[UCVTFv4f32_]]
%1:fpr(<4 x s32>) = COPY $q0
%0:fpr(<4 x s32>) = G_UITOFP %1(<4 x s32>)
@@ -4474,7 +4474,7 @@ body: |
; CHECK-LABEL: name: test_rule1649_id733_at_idx99456
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
- ; CHECK: [[UCVTFv2f64_:%[0-9]+]]:fpr128 = UCVTFv2f64 [[COPY]]
+ ; CHECK: [[UCVTFv2f64_:%[0-9]+]]:fpr128 = nofpexcept UCVTFv2f64 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[UCVTFv2f64_]]
%1:fpr(<2 x s64>) = COPY $q0
%0:fpr(<2 x s64>) = G_UITOFP %1(<2 x s64>)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select.mir
index 0cc52852378fe..dff1fadd74d45 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select.mir
@@ -185,12 +185,12 @@ registers:
- { id: 7, class: gpr }
# CHECK: body:
-# CHECK: FCMPSrr %0, %0, implicit-def $nzcv
+# CHECK: nofpexcept FCMPSrr %0, %0, implicit-def $nzcv
# CHECK: [[TST_MI:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 5, implicit $nzcv
# CHECK: [[TST_GT:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 13, implicit $nzcv
# CHECK: %1:gpr32 = ORRWrr [[TST_MI]], [[TST_GT]]
-# CHECK: FCMPDrr %2, %2, implicit-def $nzcv
+# CHECK: nofpexcept FCMPDrr %2, %2, implicit-def $nzcv
# CHECK: %3:gpr32 = CSINCWr $wzr, $wzr, 4, implicit $nzcv
body: |
diff --git a/llvm/test/CodeGen/AArch64/strict-fp-opt.ll b/llvm/test/CodeGen/AArch64/strict-fp-opt.ll
new file mode 100644
index 0000000000000..0ae05a20f4921
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/strict-fp-opt.ll
@@ -0,0 +1,78 @@
+; RUN: llc -mtriple=aarch64-none-eabi %s -o - | FileCheck %s
+; RUN: llc -mtriple=aarch64-none-eabi -global-isel=true -global-isel-abort=2 %s -o - | FileCheck %s
+
+
+; Div whose result is unused should be removed unless we have strict exceptions
+
+; CHECK-LABEL: unused_div:
+; CHECK-NOT: fdiv
+; CHECK: ret
+define void @unused_div(float %x, float %y) #0 {
+entry:
+ %add = fdiv float %x, %y
+ ret void
+}
+
+; CHECK-LABEL: unused_div_fpexcept_strict:
+; CHECK: fdiv s0, s0, s1
+; CHECK-NEXT: ret
+define void @unused_div_fpexcept_strict(float %x, float %y) #0 {
+entry:
+ %add = call float @llvm.experimental.constrained.fdiv.f32(float %x, float %y, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
+ ret void
+}
+
+
+; Machine CSE should eliminate the second add unless we have strict exceptions
+
+; CHECK-LABEL: add_twice:
+; CHECK: fadd [[ADD:s[0-9]+]], s0, s1
+; CHECK-NEXT: cmp w0, #0
+; CHECK-NEXT: fmul [[MUL:s[0-9]+]], [[ADD]], [[ADD]]
+; CHECK-NEXT: fcsel s0, [[ADD]], [[MUL]], eq
+; CHECK-NEXT: ret
+define float @add_twice(float %x, float %y, i32 %n) #0 {
+entry:
+ %add = fadd float %x, %y
+ %tobool.not = icmp eq i32 %n, 0
+ br i1 %tobool.not, label %if.end, label %if.then
+
+if.then:
+ %add1 = fadd float %x, %y
+ %mul = fmul float %add, %add1
+ br label %if.end
+
+if.end:
+ %a.0 = phi float [ %mul, %if.then ], [ %add, %entry ]
+ ret float %a.0
+}
+
+; CHECK-LABEL: add_twice_fpexcept_strict:
+; CHECK: fmov [[X:s[0-9]+]], s0
+; CHECK-NEXT: fadd s0, s0, s1
+; CHECK-NEXT: cbz w0, [[LABEL:.LBB[0-9_]+]]
+; CHECK: fadd [[ADD:s[0-9]+]], [[X]], s1
+; CHECK-NEXT: fmul s0, s0, [[ADD]]
+; CHECK: [[LABEL]]:
+; CHECK-NEXT: ret
+define float @add_twice_fpexcept_strict(float %x, float %y, i32 %n) #0 {
+entry:
+ %add = call float @llvm.experimental.constrained.fadd.f32(float %x, float %y, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
+ %tobool.not = icmp eq i32 %n, 0
+ br i1 %tobool.not, label %if.end, label %if.then
+
+if.then:
+ %add1 = call float @llvm.experimental.constrained.fadd.f32(float %x, float %y, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
+ %mul = call float @llvm.experimental.constrained.fmul.f32(float %add, float %add1, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
+ br label %if.end
+
+if.end:
+ %a.0 = phi float [ %mul, %if.then ], [ %add, %entry ]
+ ret float %a.0
+}
+
+declare float @llvm.experimental.constrained.fadd.f32(float, float, metadata, metadata) #0
+declare float @llvm.experimental.constrained.fmul.f32(float, float, metadata, metadata) #0
+declare float @llvm.experimental.constrained.fdiv.f32(float, float, metadata, metadata) #0
+
+attributes #0 = { "strictfp" }
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