[PATCH] D123322: [AArch64] Add lowerings for {ADD,SUB}CARRY and S{ADD,SUB}O_CARRY

[Karl Meakin via Phabricator via llvm-commits]

Kmeakin updated this revision to Diff 422807.
Kmeakin added a comment.

Update revision according to feedback

- Remove unecessary `{}` for single-line body.
- Pass in `Opcode` and `IsSigned` as parameters
- Explicitly check for `MVT::i32` and `MVT::i64`
- Capitalisation of `OpLHS` and `OpRHS`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123322/new/

https://reviews.llvm.org/D123322

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/adc.ll
  llvm/test/CodeGen/AArch64/addcarry-crash.ll
  llvm/test/CodeGen/AArch64/arm64-atomic-128.ll
  llvm/test/CodeGen/AArch64/arm64-vabs.ll
  llvm/test/CodeGen/AArch64/atomicrmw-O0.ll
  llvm/test/CodeGen/AArch64/i128-math.ll
  llvm/test/CodeGen/AArch64/icmp-shift-opt.ll
  llvm/test/CodeGen/AArch64/neg-abs.ll
  llvm/test/CodeGen/AArch64/neon-abd.ll
  llvm/test/CodeGen/AArch64/nzcv-save.ll
  llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
  llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
  llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
  llvm/test/CodeGen/AArch64/usub_sat_vec.ll
  llvm/test/CodeGen/AArch64/vec_uaddo.ll
  llvm/test/CodeGen/AArch64/vecreduce-add-legalization.ll

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