[PATCH] D123385: [RISCV] Precommit test for D121881

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
+
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Maybe we should be testing rv32 too?


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Comment at: llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.ll:13
+
+; Use unmasked instruction because the mask operand is allone mask;
+define <vscale x 1 x i8> @test0(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
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trailing semicolon


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Comment at: llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.ll:33
+
+; Regardless of the policy operand, TAIL_AGNOSIC is used because the tie operand is IMPLICIT_DEF
+define <vscale x 1 x i8> @test1(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
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Typo: `AGNOSIC` -> `AGNOSTIC`

Should there be a FIXME that we can use an unmasked instruction here?


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Comment at: llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.ll:55
+
+; Merge operand is kept because of the policy operand
+define <vscale x 1 x i8> @test2(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
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Again: a FIXME about unmasked instructions?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123385/new/

https://reviews.llvm.org/D123385