[llvm] 65b8a43 - [AMDGPU] Update ds-alignment.ll test checks. NFC.

[Stanislav Mekhanoshin via llvm-commits]

Author: Stanislav Mekhanoshin
Date: 2022-04-12T12:06:02-07:00
New Revision: 65b8a4324301881331373a1c339f33dd9394934e

URL: https://github.com/llvm/llvm-project/commit/65b8a4324301881331373a1c339f33dd9394934e
DIFF: https://github.com/llvm/llvm-project/commit/65b8a4324301881331373a1c339f33dd9394934e.diff

LOG: [AMDGPU] Update ds-alignment.ll test checks. NFC.

Added: 
    

Modified: 
    llvm/test/CodeGen/AMDGPU/ds-alignment.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/AMDGPU/ds-alignment.ll b/llvm/test/CodeGen/AMDGPU/ds-alignment.ll
index f6ff94e2406b0..e3b6dce9f9213 100644
--- a/llvm/test/CodeGen/AMDGPU/ds-alignment.ll
+++ b/llvm/test/CodeGen/AMDGPU/ds-alignment.ll
@@ -1,8 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx900 -mattr=-unaligned-access-mode < %s | FileCheck %s -check-prefixes=GCN,ALIGNED,ALIGNED-SDAG
 ; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx900 -mattr=-unaligned-access-mode < %s | FileCheck %s -check-prefixes=GCN,ALIGNED,ALIGNED-GISEL
-; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx900 -mattr=+unaligned-access-mode < %s | FileCheck %s -check-prefixes=GCN,UNALIGNED
-; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx900 -mattr=+unaligned-access-mode < %s | FileCheck %s -check-prefixes=GCN,UNALIGNED
+; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx900 -mattr=+unaligned-access-mode < %s | FileCheck %s -check-prefixes=GCN,UNALIGNED,UNALIGNED-SDAG
+; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx900 -mattr=+unaligned-access-mode < %s | FileCheck %s -check-prefixes=GCN,UNALIGNED,UNALIGNED-GISEL
 
 define amdgpu_kernel void @ds1align1(i8 addrspace(3)* %in, i8 addrspace(3)* %out) {
 ; GCN-LABEL: ds1align1:
@@ -566,6 +566,31 @@ define amdgpu_kernel void @ds12align4(<3 x i32> addrspace(3)* %in, <3 x i32> add
 ; ALIGNED-NEXT:    s_waitcnt lgkmcnt(1)
 ; ALIGNED-NEXT:    ds_write_b32 v3, v2 offset:8
 ; ALIGNED-NEXT:    s_endpgm
+;
+; UNALIGNED-SDAG-LABEL: ds12align4:
+; UNALIGNED-SDAG:       ; %bb.0:
+; UNALIGNED-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; UNALIGNED-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
+; UNALIGNED-SDAG-NEXT:    v_mov_b32_e32 v2, s0
+; UNALIGNED-SDAG-NEXT:    ds_read2_b32 v[0:1], v2 offset1:1
+; UNALIGNED-SDAG-NEXT:    ds_read_b32 v2, v2 offset:8
+; UNALIGNED-SDAG-NEXT:    v_mov_b32_e32 v3, s1
+; UNALIGNED-SDAG-NEXT:    s_waitcnt lgkmcnt(1)
+; UNALIGNED-SDAG-NEXT:    ds_write2_b32 v3, v0, v1 offset1:1
+; UNALIGNED-SDAG-NEXT:    s_waitcnt lgkmcnt(1)
+; UNALIGNED-SDAG-NEXT:    ds_write_b32 v3, v2 offset:8
+; UNALIGNED-SDAG-NEXT:    s_endpgm
+;
+; UNALIGNED-GISEL-LABEL: ds12align4:
+; UNALIGNED-GISEL:       ; %bb.0:
+; UNALIGNED-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; UNALIGNED-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; UNALIGNED-GISEL-NEXT:    v_mov_b32_e32 v0, s0
+; UNALIGNED-GISEL-NEXT:    ds_read_b96 v[0:2], v0
+; UNALIGNED-GISEL-NEXT:    v_mov_b32_e32 v3, s1
+; UNALIGNED-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; UNALIGNED-GISEL-NEXT:    ds_write_b96 v3, v[0:2]
+; UNALIGNED-GISEL-NEXT:    s_endpgm
   %val = load <3 x i32>, <3 x i32> addrspace(3)* %in, align 4
   store <3 x i32> %val, <3 x i32> addrspace(3)* %out, align 4
   ret void
@@ -599,6 +624,31 @@ define amdgpu_kernel void @ds12align8(<3 x i32> addrspace(3)* %in, <3 x i32> add
 ; ALIGNED-GISEL-NEXT:    s_waitcnt lgkmcnt(1)
 ; ALIGNED-GISEL-NEXT:    ds_write_b32 v3, v2 offset:8
 ; ALIGNED-GISEL-NEXT:    s_endpgm
+;
+; UNALIGNED-SDAG-LABEL: ds12align8:
+; UNALIGNED-SDAG:       ; %bb.0:
+; UNALIGNED-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; UNALIGNED-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
+; UNALIGNED-SDAG-NEXT:    v_mov_b32_e32 v0, s0
+; UNALIGNED-SDAG-NEXT:    ds_read_b32 v2, v0 offset:8
+; UNALIGNED-SDAG-NEXT:    ds_read_b64 v[0:1], v0
+; UNALIGNED-SDAG-NEXT:    v_mov_b32_e32 v3, s1
+; UNALIGNED-SDAG-NEXT:    s_waitcnt lgkmcnt(1)
+; UNALIGNED-SDAG-NEXT:    ds_write_b32 v3, v2 offset:8
+; UNALIGNED-SDAG-NEXT:    s_waitcnt lgkmcnt(1)
+; UNALIGNED-SDAG-NEXT:    ds_write_b64 v3, v[0:1]
+; UNALIGNED-SDAG-NEXT:    s_endpgm
+;
+; UNALIGNED-GISEL-LABEL: ds12align8:
+; UNALIGNED-GISEL:       ; %bb.0:
+; UNALIGNED-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; UNALIGNED-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; UNALIGNED-GISEL-NEXT:    v_mov_b32_e32 v0, s0
+; UNALIGNED-GISEL-NEXT:    ds_read_b96 v[0:2], v0
+; UNALIGNED-GISEL-NEXT:    v_mov_b32_e32 v3, s1
+; UNALIGNED-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; UNALIGNED-GISEL-NEXT:    ds_write_b96 v3, v[0:2]
+; UNALIGNED-GISEL-NEXT:    s_endpgm
   %val = load <3 x i32>, <3 x i32> addrspace(3)* %in, align 8
   store <3 x i32> %val, <3 x i32> addrspace(3)* %out, align 8
   ret void