[PATCH] D123620: AArch64/GlobalISel: Stop using legal s1 values

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: paquette, aemerson.
Herald added subscribers: hiraditya, kristof.beyls, rovka.
Herald added a project: All.
arsenm requested review of this revision.
Herald added a subscriber: wdng.
Herald added a project: LLVM.

As far as I can tell treating s1 values as legal makes no sense. There
are no allocatable 1-bit registers. SelectionDAG legalizes the usual
set of boolean operations to 32-bits, and this should do the
same. This avoids some special case handling in the selector of s1
values, and some extra code to look through truncates.

      

This makes some code worse at -O0, since nothing cleans up the and 1
the artifact combiner inserts. We could probably add some
non-essential combines or teach the artifact combiner to elide
intermediates betweeen boolean uses and defs.


https://reviews.llvm.org/D123620

Files:
  llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
  llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
  llvm/test/CodeGen/AArch64/GlobalISel/fold-brcond-fcmp.mir
  llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir
  llvm/test/CodeGen/AArch64/GlobalISel/fold-select.mir
  llvm/test/CodeGen/AArch64/GlobalISel/huge-switch.ll
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-freeze.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-min-max.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-sadde.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddo.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddsat.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssube.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubo.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubsat.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadd-sat.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadde.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-uaddo.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-usub-sat.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-usube.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-usubo.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir
  llvm/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll
  llvm/test/CodeGen/AArch64/GlobalISel/opt-and-tbnz-tbz.mir
  llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-and-tbz-tbnz.mir
  llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-compare.mir
  llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-ext-tbz-tbnz.mir
  llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-shift-tbz-tbnz.mir
  llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-trunc-tbz-tbnz.mir
  llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-xor-tbz-tbnz.mir
  llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-adjust-icmp-imm.mir
  llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir
  llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir
  llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-zext.mir
  llvm/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir
  llvm/test/CodeGen/AArch64/GlobalISel/regbank-select.mir
  llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-br.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-brcond-of-binop.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-phi.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-saddo.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-ssubo.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-static.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-truncstore-atomic.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-uaddo.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select-usubo.mir
  llvm/test/CodeGen/AArch64/GlobalISel/select.mir
  llvm/test/CodeGen/AArch64/GlobalISel/speculative-hardening-brcond.mir
  llvm/test/CodeGen/AArch64/GlobalISel/subreg-copy.mir
  llvm/test/CodeGen/AArch64/GlobalISel/tbnz-slt.mir
  llvm/test/CodeGen/AArch64/GlobalISel/tbz-sgt.mir
  llvm/test/CodeGen/AArch64/GlobalISel/widen-narrow-tbz-tbnz.mir
  llvm/test/CodeGen/AArch64/arm64-xaluo.ll

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