[PATCH] D123581: [RISCV] Teach vsetvli insertion to handle VSETVLIInfo of vl-modified instruction.
Yeting Kuo via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 12 02:55:13 PDT 2022
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If an instruction's AVL is a copy of resulted VL of a instruction,
the instruction have same VL if both of them have same Vtype. The patch adds a
new status, VLModified, to avoid consider the VSETVLIInfo of vl-modified
instructions unknonwn and do not insert vsetsvli if the instruction's AVL is
a copy of resulted VL of last instructions.
Take the below C code as an example,
vint8m4_t vec_src1 = vle8ff_v_i8m4(str1, &new_vl, vl);
vbool2_t mask1 = vmseq_vx_i8m4_b2(vec_src1, 0, new_vl);
Vsetvli insertion adds a redundant vsetvli for that,
vsetvli a2,a2,e8,m4,ta,mu
vle8ff.v v28,(a0)
csrr a3,vl ; redundant
vsetvli zero,a3,e8,m4,ta,mu ; redundant
vmseq.vi v25,v28,0
Although the patch could prevent some redundant vsetvli, those PseudoReadVL
could not be optimized since the pass followed by register allocation.
We could re-run some optimization pass like dead-mi-elimination to solve the
problem.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D123581
Files:
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
llvm/test/CodeGen/RISCV/rvv/vsetvli-modify-vl.ll
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