[PATCH] D123523: [DAG] Add non-uniform vector support to (shl (srl x, c1), c2) -> (and (shift x, c3))

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon updated this revision to Diff 422150.
RKSimon added a comment.

Ensure we test up to the max shift bounds and merge shl(shl(x,N01),sub(N1,N01)) shifts


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123523/new/

https://reviews.llvm.org/D123523

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/X86/combine-shl.ll
  llvm/test/CodeGen/X86/rotate-extract-vector.ll

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