[PATCH] D123577: WIP [MIPS][SelectionDAG] Enable TargetLowering::hasBitTest for masks that fit in ANDI.
LiqinWeng via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 12 02:17:58 PDT 2022
Miss_Grape created this revision.
Miss_Grape added reviewers: benshi001, craig.topper.
Herald added subscribers: StephenFan, ecnelises, atanasyan, jrtc27, hiraditya, arichardson, sdardis.
Herald added a project: All.
Miss_Grape requested review of this revision.
Herald added subscribers: llvm-commits, jacquesguan.
Herald added a project: LLVM.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D123577
Files:
llvm/lib/Target/Mips/MipsISelLowering.cpp
llvm/lib/Target/Mips/MipsISelLowering.h
Index: llvm/lib/Target/Mips/MipsISelLowering.h
===================================================================
--- llvm/lib/Target/Mips/MipsISelLowering.h
+++ llvm/lib/Target/Mips/MipsISelLowering.h
@@ -282,6 +282,7 @@
bool isCheapToSpeculateCttz() const override;
bool isCheapToSpeculateCtlz() const override;
+ bool hasBitTest(SDValue X, SDValue Y) const override;
bool shouldFoldConstantShiftPairToMask(const SDNode *N,
CombineLevel Level) const override;
Index: llvm/lib/Target/Mips/MipsISelLowering.cpp
===================================================================
--- llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -1174,6 +1174,12 @@
return Subtarget.hasMips32();
}
+bool MipsTargetLowering::hasBitTest(SDValue X, SDValue Y) const {
+ // We can use ANDI+SEQZ/SNEZ as a bit test. Y contains the bit position.
+ auto *C = dyn_cast<ConstantSDNode>(Y);
+ return C && C->getAPIntValue().ule(14);
+}
+
bool MipsTargetLowering::shouldFoldConstantShiftPairToMask(
const SDNode *N, CombineLevel Level) const {
if (N->getOperand(0).getValueType().isVector())
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