[PATCH] D123523: [DAG] Add non-uniform vector support to (shl (srl x, c1), c2) -> (and (shift x, c3))

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:8948
+      SDValue Mask = DAG.getAllOnesConstant(DL, VT);
+      Mask = DAG.getNode(ISD::SHL, DL, VT, Mask, N01);
+      Mask = DAG.getNode(ISD::SHL, DL, VT, Mask, Diff);
----------------
Can these two SHL of mask be replaced with

```
Mask = DAG.getNode(ISD::SHL, DL, VT, Mask, N1)
```

As far as I can tell we're shifting by N01 + (N1 - N01) which should just be N1?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123523/new/

https://reviews.llvm.org/D123523