[llvm] 4c037bd - AMDGPU/GlobalISel: Add more tests for inreg extend + load combine
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 11 16:44:41 PDT 2022
Author: Matt Arsenault
Date: 2022-04-11T19:43:37-04:00
New Revision: 4c037bdbab29e29ae371c6c9370b49b5b8d75ec9
URL: https://github.com/llvm/llvm-project/commit/4c037bdbab29e29ae371c6c9370b49b5b8d75ec9
DIFF: https://github.com/llvm/llvm-project/commit/4c037bdbab29e29ae371c6c9370b49b5b8d75ec9.diff
LOG: AMDGPU/GlobalISel: Add more tests for inreg extend + load combine
Added:
llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-zextload-from-and.mir
Modified:
llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-sextload-from-sextinreg.mir
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-sextload-from-sextinreg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-sextload-from-sextinreg.mir
index 573094c7335b9..80cd9e8ff55a9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-sextload-from-sextinreg.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-sextload-from-sextinreg.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs -o - %s | FileCheck %s
# Post-legalizer should not generate illegal extending loads
---
@@ -21,3 +21,161 @@ body: |
%2:_(s64) = G_SEXT_INREG %1, 8
$vgpr0_vgpr1 = COPY %2
...
+
+# Legal to fold into sextload
+---
+name: sext_inreg_8_sextload_s32
+tracksRegLiveness: true
+legalized: true
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+ ; CHECK-LABEL: name: sext_inreg_8_sextload_s32
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load (s8), align 4, addrspace 1)
+ ; CHECK-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_LOAD %0 :: (load (s32), align 4, addrspace 1)
+ %2:_(s32) = G_SEXT_INREG %1, 8
+ $vgpr0 = COPY %2
+...
+
+---
+name: sext_inreg_7_sextload_s32
+tracksRegLiveness: true
+legalized: true
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+ ; CHECK-LABEL: name: sext_inreg_7_sextload_s32
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LOAD]], 7
+ ; CHECK-NEXT: $vgpr0 = COPY [[SEXT_INREG]](s32)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_LOAD %0 :: (load (s32), align 4, addrspace 1)
+ %2:_(s32) = G_SEXT_INREG %1, 7
+ $vgpr0 = COPY %2
+...
+
+---
+name: sext_inreg_9_sextload_s32
+tracksRegLiveness: true
+legalized: true
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+ ; CHECK-LABEL: name: sext_inreg_9_sextload_s32
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LOAD]], 9
+ ; CHECK-NEXT: $vgpr0 = COPY [[SEXT_INREG]](s32)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_LOAD %0 :: (load (s32), align 4, addrspace 1)
+ %2:_(s32) = G_SEXT_INREG %1, 9
+ $vgpr0 = COPY %2
+...
+
+# Legal to fold into sextload
+---
+name: sext_inreg_16_sextload_s32
+tracksRegLiveness: true
+legalized: true
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+ ; CHECK-LABEL: name: sext_inreg_16_sextload_s32
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
+ ; CHECK-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_LOAD %0 :: (load (s32), align 4, addrspace 1)
+ %2:_(s32) = G_SEXT_INREG %1, 16
+ $vgpr0 = COPY %2
+...
+
+---
+name: sext_inreg_8_sextload_s8
+tracksRegLiveness: true
+legalized: true
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+ ; CHECK-LABEL: name: sext_inreg_8_sextload_s8
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 1)
+ ; CHECK-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_LOAD %0 :: (load (s8), align 1, addrspace 1)
+ %2:_(s32) = G_SEXT_INREG %1, 8
+ $vgpr0 = COPY %2
+...
+
+---
+name: sext_inreg_8_sextload_s8_volatile
+tracksRegLiveness: true
+legalized: true
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+ ; CHECK-LABEL: name: sext_inreg_8_sextload_s8_volatile
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (volatile load (s8), addrspace 1)
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LOAD]], 8
+ ; CHECK-NEXT: $vgpr0 = COPY [[SEXT_INREG]](s32)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_LOAD %0 :: (volatile load (s8), align 1, addrspace 1)
+ %2:_(s32) = G_SEXT_INREG %1, 8
+ $vgpr0 = COPY %2
+...
+
+---
+name: sext_inreg_16_sextload_s16
+tracksRegLiveness: true
+legalized: true
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+ ; CHECK-LABEL: name: sext_inreg_16_sextload_s16
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load (s16), addrspace 1)
+ ; CHECK-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_LOAD %0 :: (load (s16), align 2, addrspace 1)
+ %2:_(s32) = G_SEXT_INREG %1, 16
+ $vgpr0 = COPY %2
+...
+
+---
+name: sext_inreg_16_sextload_s16_volatile
+tracksRegLiveness: true
+legalized: true
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+ ; CHECK-LABEL: name: sext_inreg_16_sextload_s16_volatile
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (volatile load (s16), addrspace 1)
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[LOAD]], 16
+ ; CHECK-NEXT: $vgpr0 = COPY [[SEXT_INREG]](s32)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_LOAD %0 :: (volatile load (s16), align 2, addrspace 1)
+ %2:_(s32) = G_SEXT_INREG %1, 16
+ $vgpr0 = COPY %2
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-zextload-from-and.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-zextload-from-and.mir
new file mode 100644
index 0000000000000..0b55aec8bef93
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-zextload-from-and.mir
@@ -0,0 +1,195 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs -o - %s | FileCheck %s
+
+# Post-legalizer should not generate illegal extending loads
+---
+name: zextload_from_inreg
+tracksRegLiveness: true
+legalized: true
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+ ; CHECK-LABEL: name: zextload_from_inreg
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p1) :: (load (s64), addrspace 1)
+ ; CHECK-NEXT: %k:_(s64) = G_CONSTANT i64 4294967295
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[LOAD]], %k
+ ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[AND]](s64)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s64) = G_LOAD %0 :: (load (s64), align 8, addrspace 1)
+ %k:_(s64) = G_CONSTANT i64 4294967295
+ %2:_(s64) = G_AND %1, %k
+ $vgpr0_vgpr1 = COPY %2
+...
+
+# Legal to fold into zextload
+---
+name: zext_inreg_8_zextload_s32
+tracksRegLiveness: true
+legalized: true
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+ ; CHECK-LABEL: name: zext_inreg_8_zextload_s32
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s8), align 4, addrspace 1)
+ ; CHECK-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_LOAD %0 :: (load (s32), align 4, addrspace 1)
+ %k:_(s32) = G_CONSTANT i32 255
+ %2:_(s32) = G_AND %1, %k
+ $vgpr0 = COPY %2
+...
+
+---
+name: zext_inreg_7_zextload_s32
+tracksRegLiveness: true
+legalized: true
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+ ; CHECK-LABEL: name: zext_inreg_7_zextload_s32
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
+ ; CHECK-NEXT: %k:_(s32) = G_CONSTANT i32 127
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], %k
+ ; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_LOAD %0 :: (load (s32), align 4, addrspace 1)
+ %k:_(s32) = G_CONSTANT i32 127
+ %2:_(s32) = G_AND %1, %k
+ $vgpr0 = COPY %2
+...
+
+---
+name: zext_inreg_9_zextload_s32
+tracksRegLiveness: true
+legalized: true
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+ ; CHECK-LABEL: name: zext_inreg_9_zextload_s32
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
+ ; CHECK-NEXT: %k:_(s32) = G_CONSTANT i32 511
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], %k
+ ; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_LOAD %0 :: (load (s32), align 4, addrspace 1)
+ %k:_(s32) = G_CONSTANT i32 511
+ %2:_(s32) = G_AND %1, %k
+ $vgpr0 = COPY %2
+...
+
+# Legal to fold into zextload
+---
+name: zext_inreg_16_zextload_s32
+tracksRegLiveness: true
+legalized: true
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+ ; CHECK-LABEL: name: zext_inreg_16_zextload_s32
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
+ ; CHECK-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_LOAD %0 :: (load (s32), align 4, addrspace 1)
+ %k:_(s32) = G_CONSTANT i32 65535
+ %2:_(s32) = G_AND %1, %k
+ $vgpr0 = COPY %2
+...
+
+---
+name: zext_inreg_8_zextload_s8
+tracksRegLiveness: true
+legalized: true
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+ ; CHECK-LABEL: name: zext_inreg_8_zextload_s8
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 1)
+ ; CHECK-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_LOAD %0 :: (load (s8), align 1, addrspace 1)
+ %k:_(s32) = G_CONSTANT i32 255
+ %2:_(s32) = G_AND %1, %k
+ $vgpr0 = COPY %2
+...
+
+---
+name: zext_inreg_8_zextload_s8_volatile
+tracksRegLiveness: true
+legalized: true
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+ ; CHECK-LABEL: name: zext_inreg_8_zextload_s8_volatile
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (volatile load (s8), addrspace 1)
+ ; CHECK-NEXT: %k:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], %k
+ ; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_LOAD %0 :: (volatile load (s8), align 1, addrspace 1)
+ %k:_(s32) = G_CONSTANT i32 255
+ %2:_(s32) = G_AND %1, %k
+ $vgpr0 = COPY %2
+...
+
+---
+name: zext_inreg_16_zextload_s16
+tracksRegLiveness: true
+legalized: true
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+ ; CHECK-LABEL: name: zext_inreg_16_zextload_s16
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s16), addrspace 1)
+ ; CHECK-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_LOAD %0 :: (load (s16), align 2, addrspace 1)
+ %k:_(s32) = G_CONSTANT i32 65535
+ %2:_(s32) = G_AND %1, %k
+ $vgpr0 = COPY %2
+...
+
+---
+name: zext_inreg_16_zextload_s16_volatile
+tracksRegLiveness: true
+legalized: true
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+ ; CHECK-LABEL: name: zext_inreg_16_zextload_s16_volatile
+ ; CHECK: liveins: $vgpr0_vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (volatile load (s16), addrspace 1)
+ ; CHECK-NEXT: %k:_(s32) = G_CONSTANT i32 65535
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], %k
+ ; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)
+ %0:_(p1) = COPY $vgpr0_vgpr1
+ %1:_(s32) = G_LOAD %0 :: (volatile load (s16), align 2, addrspace 1)
+ %k:_(s32) = G_CONSTANT i32 65535
+ %2:_(s32) = G_AND %1, %k
+ $vgpr0 = COPY %2
+...
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