[llvm] 463bc93 - AMDGPU/GlobalISel: Remove unused parameter
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 11 16:44:35 PDT 2022
Author: Matt Arsenault
Date: 2022-04-11T19:43:37-04:00
New Revision: 463bc93e5f57729d4bd7c5478f1e634987188514
URL: https://github.com/llvm/llvm-project/commit/463bc93e5f57729d4bd7c5478f1e634987188514
DIFF: https://github.com/llvm/llvm-project/commit/463bc93e5f57729d4bd7c5478f1e634987188514.diff
LOG: AMDGPU/GlobalISel: Remove unused parameter
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 31e3cd6c3e581..c833fc174ca4c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -217,7 +217,7 @@ bool AMDGPUInstructionSelector::selectPHI(MachineInstr &I) const {
}
const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>();
- DefRC = TRI.getRegClassForTypeOnBank(DefTy, RB, *MRI);
+ DefRC = TRI.getRegClassForTypeOnBank(DefTy, RB);
if (!DefRC) {
LLVM_DEBUG(dbgs() << "PHI operand has unexpected size/bank\n");
return false;
@@ -482,7 +482,7 @@ bool AMDGPUInstructionSelector::selectG_EXTRACT(MachineInstr &I) const {
const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, *MRI, TRI);
const TargetRegisterClass *SrcRC =
- TRI.getRegClassForSizeOnBank(SrcSize, *SrcBank, *MRI);
+ TRI.getRegClassForSizeOnBank(SrcSize, *SrcBank);
if (!SrcRC)
return false;
unsigned SubReg = SIRegisterInfo::getSubRegFromChannel(Offset / 32,
@@ -515,7 +515,7 @@ bool AMDGPUInstructionSelector::selectG_MERGE_VALUES(MachineInstr &MI) const {
const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI);
const unsigned DstSize = DstTy.getSizeInBits();
const TargetRegisterClass *DstRC =
- TRI.getRegClassForSizeOnBank(DstSize, *DstBank, *MRI);
+ TRI.getRegClassForSizeOnBank(DstSize, *DstBank);
if (!DstRC)
return false;
@@ -557,7 +557,7 @@ bool AMDGPUInstructionSelector::selectG_UNMERGE_VALUES(MachineInstr &MI) const {
const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, *MRI, TRI);
const TargetRegisterClass *SrcRC =
- TRI.getRegClassForSizeOnBank(SrcSize, *SrcBank, *MRI);
+ TRI.getRegClassForSizeOnBank(SrcSize, *SrcBank);
if (!SrcRC || !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI))
return false;
@@ -723,16 +723,16 @@ bool AMDGPUInstructionSelector::selectG_INSERT(MachineInstr &I) const {
const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI);
const TargetRegisterClass *DstRC =
- TRI.getRegClassForSizeOnBank(DstSize, *DstBank, *MRI);
+ TRI.getRegClassForSizeOnBank(DstSize, *DstBank);
if (!DstRC)
return false;
const RegisterBank *Src0Bank = RBI.getRegBank(Src0Reg, *MRI, TRI);
const RegisterBank *Src1Bank = RBI.getRegBank(Src1Reg, *MRI, TRI);
const TargetRegisterClass *Src0RC =
- TRI.getRegClassForSizeOnBank(DstSize, *Src0Bank, *MRI);
+ TRI.getRegClassForSizeOnBank(DstSize, *Src0Bank);
const TargetRegisterClass *Src1RC =
- TRI.getRegClassForSizeOnBank(InsSize, *Src1Bank, *MRI);
+ TRI.getRegClassForSizeOnBank(InsSize, *Src1Bank);
// Deal with weird cases where the class only partially supports the subreg
// index.
@@ -1172,8 +1172,7 @@ bool AMDGPUInstructionSelector::selectBallot(MachineInstr &I) const {
bool AMDGPUInstructionSelector::selectRelocConstant(MachineInstr &I) const {
Register DstReg = I.getOperand(0).getReg();
const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI);
- const TargetRegisterClass *DstRC =
- TRI.getRegClassForSizeOnBank(32, *DstBank, *MRI);
+ const TargetRegisterClass *DstRC = TRI.getRegClassForSizeOnBank(32, *DstBank);
if (!DstRC || !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI))
return false;
@@ -1880,10 +1879,10 @@ bool AMDGPUInstructionSelector::selectG_TRUNC(MachineInstr &I) const {
unsigned DstSize = DstTy.getSizeInBits();
unsigned SrcSize = SrcTy.getSizeInBits();
- const TargetRegisterClass *SrcRC
- = TRI.getRegClassForSizeOnBank(SrcSize, *SrcRB, *MRI);
- const TargetRegisterClass *DstRC
- = TRI.getRegClassForSizeOnBank(DstSize, *DstRB, *MRI);
+ const TargetRegisterClass *SrcRC =
+ TRI.getRegClassForSizeOnBank(SrcSize, *SrcRB);
+ const TargetRegisterClass *DstRC =
+ TRI.getRegClassForSizeOnBank(DstSize, *DstRB);
if (!SrcRC || !DstRC)
return false;
@@ -2022,10 +2021,10 @@ bool AMDGPUInstructionSelector::selectG_SZA_EXT(MachineInstr &I) const {
return selectCOPY(I);
const TargetRegisterClass *SrcRC =
- TRI.getRegClassForTypeOnBank(SrcTy, *SrcBank, *MRI);
+ TRI.getRegClassForTypeOnBank(SrcTy, *SrcBank);
const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI);
const TargetRegisterClass *DstRC =
- TRI.getRegClassForSizeOnBank(DstSize, *DstBank, *MRI);
+ TRI.getRegClassForSizeOnBank(DstSize, *DstBank);
Register UndefReg = MRI->createVirtualRegister(SrcRC);
BuildMI(MBB, I, DL, TII.get(AMDGPU::IMPLICIT_DEF), UndefReg);
@@ -2520,12 +2519,10 @@ bool AMDGPUInstructionSelector::selectG_PTRMASK(MachineInstr &I) const {
const TargetRegisterClass &RegRC
= IsVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::SReg_32RegClass;
- const TargetRegisterClass *DstRC = TRI.getRegClassForTypeOnBank(Ty, *DstRB,
- *MRI);
- const TargetRegisterClass *SrcRC = TRI.getRegClassForTypeOnBank(Ty, *SrcRB,
- *MRI);
+ const TargetRegisterClass *DstRC = TRI.getRegClassForTypeOnBank(Ty, *DstRB);
+ const TargetRegisterClass *SrcRC = TRI.getRegClassForTypeOnBank(Ty, *SrcRB);
const TargetRegisterClass *MaskRC =
- TRI.getRegClassForTypeOnBank(MaskTy, *MaskRB, *MRI);
+ TRI.getRegClassForTypeOnBank(MaskTy, *MaskRB);
if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI) ||
!RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI) ||
@@ -2638,10 +2635,10 @@ bool AMDGPUInstructionSelector::selectG_EXTRACT_VECTOR_ELT(
if (IdxRB->getID() != AMDGPU::SGPRRegBankID)
return false;
- const TargetRegisterClass *SrcRC = TRI.getRegClassForTypeOnBank(SrcTy, *SrcRB,
- *MRI);
- const TargetRegisterClass *DstRC = TRI.getRegClassForTypeOnBank(DstTy, *DstRB,
- *MRI);
+ const TargetRegisterClass *SrcRC =
+ TRI.getRegClassForTypeOnBank(SrcTy, *SrcRB);
+ const TargetRegisterClass *DstRC =
+ TRI.getRegClassForTypeOnBank(DstTy, *DstRB);
if (!SrcRC || !DstRC)
return false;
if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI) ||
@@ -2720,10 +2717,10 @@ bool AMDGPUInstructionSelector::selectG_INSERT_VECTOR_ELT(
if (IdxRB->getID() != AMDGPU::SGPRRegBankID)
return false;
- const TargetRegisterClass *VecRC = TRI.getRegClassForTypeOnBank(VecTy, *VecRB,
- *MRI);
- const TargetRegisterClass *ValRC = TRI.getRegClassForTypeOnBank(ValTy, *ValRB,
- *MRI);
+ const TargetRegisterClass *VecRC =
+ TRI.getRegClassForTypeOnBank(VecTy, *VecRB);
+ const TargetRegisterClass *ValRC =
+ TRI.getRegClassForTypeOnBank(ValTy, *ValRB);
if (!RBI.constrainGenericRegister(VecReg, *VecRC, *MRI) ||
!RBI.constrainGenericRegister(DstReg, *VecRC, *MRI) ||
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index deeaee928f7f3..9321828299e1e 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -2902,8 +2902,7 @@ MCRegister SIRegisterInfo::getReturnAddressReg(const MachineFunction &MF) const
const TargetRegisterClass *
SIRegisterInfo::getRegClassForSizeOnBank(unsigned Size,
- const RegisterBank &RB,
- const MachineRegisterInfo &MRI) const {
+ const RegisterBank &RB) const {
switch (RB.getID()) {
case AMDGPU::VGPRRegBankID:
return getVGPRClassForBitWidth(std::max(32u, Size));
@@ -2925,7 +2924,7 @@ SIRegisterInfo::getConstrainedRegClassForOperand(const MachineOperand &MO,
const MachineRegisterInfo &MRI) const {
const RegClassOrRegBank &RCOrRB = MRI.getRegClassOrRegBank(MO.getReg());
if (const RegisterBank *RB = RCOrRB.dyn_cast<const RegisterBank*>())
- return getRegClassForTypeOnBank(MRI.getType(MO.getReg()), *RB, MRI);
+ return getRegClassForTypeOnBank(MRI.getType(MO.getReg()), *RB);
if (const auto *RC = RCOrRB.dyn_cast<const TargetRegisterClass *>())
return getAllocatableClass(RC);
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index 93b1c65e2ebec..2f3b489a49328 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -306,15 +306,11 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
MCRegister getReturnAddressReg(const MachineFunction &MF) const;
const TargetRegisterClass *
- getRegClassForSizeOnBank(unsigned Size,
- const RegisterBank &Bank,
- const MachineRegisterInfo &MRI) const;
+ getRegClassForSizeOnBank(unsigned Size, const RegisterBank &Bank) const;
const TargetRegisterClass *
- getRegClassForTypeOnBank(LLT Ty,
- const RegisterBank &Bank,
- const MachineRegisterInfo &MRI) const {
- return getRegClassForSizeOnBank(Ty.getSizeInBits(), Bank, MRI);
+ getRegClassForTypeOnBank(LLT Ty, const RegisterBank &Bank) const {
+ return getRegClassForSizeOnBank(Ty.getSizeInBits(), Bank);
}
const TargetRegisterClass *
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