[PATCH] D123553: [RISCV] Add a encodeLMUL function to RISCVVType. NFC
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 11 15:58:12 PDT 2022
craig.topper created this revision.
craig.topper added reviewers: kito-cheng, khchen, arcbbb, frasercrmck, rogfer01.
Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya, arichardson.
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Herald added subscribers: pcwang-thead, eopXD, MaskRay.
Herald added a project: LLVM.
This moves the encoding handling out of the assembly parser.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D123553
Files:
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
===================================================================
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -383,6 +383,12 @@
// Decode VLMUL into 1,2,4,8 and fractional indicator.
std::pair<unsigned, bool> decodeVLMUL(RISCVII::VLMUL VLMUL);
+inline static RISCVII::VLMUL encodeLMUL(unsigned LMUL, bool Fractional) {
+ assert(isValidLMUL(LMUL, Fractional) && "Unsupported LMUL");
+ unsigned LmulLog2 = Log2_32(LMUL);
+ return static_cast<RISCVII::VLMUL>(Fractional ? 8 - LmulLog2 : LmulLog2);
+}
+
inline static unsigned decodeVSEW(unsigned VSEW) {
assert(VSEW < 8 && "Unexpected VSEW value");
return 1 << (VSEW + 3);
Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===================================================================
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1776,9 +1776,7 @@
else
goto MatchFail;
- unsigned LmulLog2 = Log2_32(Lmul);
- RISCVII::VLMUL VLMUL =
- static_cast<RISCVII::VLMUL>(Fractional ? 8 - LmulLog2 : LmulLog2);
+ RISCVII::VLMUL VLMUL = RISCVVType::encodeLMUL(Lmul, Fractional);
unsigned VTypeI =
RISCVVType::encodeVTYPE(VLMUL, Sew, TailAgnostic, MaskAgnostic);
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