[llvm] 6c85668 - Tail calls: look through AssertZExt to find register copy.

[Tim Northover via llvm-commits]

Author: Tim Northover
Date: 2022-04-11T12:24:47+01:00
New Revision: 6c85668d280408c0920f64fa1c791861faf358c4

URL: https://github.com/llvm/llvm-project/commit/6c85668d280408c0920f64fa1c791861faf358c4
DIFF: https://github.com/llvm/llvm-project/commit/6c85668d280408c0920f64fa1c791861faf358c4.diff

LOG: Tail calls: look through AssertZExt to find register copy.

arm64_32 guarantees the high 32 bits of pointer parameters are passed as 0, and
this is modelled in the IR by inserting an AssertZExt after the CopyFromReg.
The function deciding whether registers that need to be preserved actually are
wasn't expecting this so it banned perfectly legitimate tail calls.

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    llvm/test/CodeGen/AArch64/swiftself.ll

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 345c79c8d357e..58f5ae44ed52a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -92,6 +92,8 @@ bool TargetLowering::parametersInCSRMatch(const MachineRegisterInfo &MRI,
     // (We look for a CopyFromReg reading a virtual register that is used
     //  for the function live-in value of register Reg)
     SDValue Value = OutVals[I];
+    if (Value->getOpcode() == ISD::AssertZext)
+      Value = Value.getOperand(0);
     if (Value->getOpcode() != ISD::CopyFromReg)
       return false;
     Register ArgReg = cast<RegisterSDNode>(Value->getOperand(1))->getReg();

diff  --git a/llvm/test/CodeGen/AArch64/swiftself.ll b/llvm/test/CodeGen/AArch64/swiftself.ll
index d645b0a9bf437..544f4471e9817 100644
--- a/llvm/test/CodeGen/AArch64/swiftself.ll
+++ b/llvm/test/CodeGen/AArch64/swiftself.ll
@@ -51,10 +51,10 @@ define void @swiftself_passthrough(i8* swiftself %addr0) {
 ; CHECK-LABEL: swiftself_tail:
 ; OPTAARCH64: b {{_?}}swiftself_param
 ; OPTAARCH64-NOT: ret
-; OPTARM64_32: bl {{_?}}swiftself_param
+; OPTARM64_32: b {{_?}}swiftself_param
 define i8* @swiftself_tail(i8* swiftself %addr0) {
   call void asm sideeffect "", "~{x20}"()
-  %res = tail call i8* @swiftself_param(i8* swiftself %addr0)
+  %res = musttail call i8* @swiftself_param(i8* swiftself %addr0)
   ret i8* %res
 }