[PATCH] D123458: [LSR][RISCV] Improve test coverage for LSR in RISC-V

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/loop-strength-reduce.ll:7
+
+define void @test(i32 %row, i32 %N.in) nounwind {
+; RV32-LABEL: test:
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Can we add `signext` attributes to the i32 arguments to match the ABI for rv64 and remove some extra sext.w


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123458/new/

https://reviews.llvm.org/D123458