[PATCH] D123458: [LSR][RISCV] Improve test coverage for LSR in RISC-V

[Yueh-Ting (eop) Chen via Phabricator via llvm-commits]

eopXD created this revision.
eopXD added reviewers: joshua-arch1, asb, craig.topper.
Herald added subscribers: sunshaoce, VincentWu, luke957, StephenFan, vkmr, evandro, luismarques, sameer.abuasal, pengfei, s.egerton, Jim, benna, psnobl, rogfer01, kito-cheng, simoncook, arichardson.
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Herald added a project: LLVM.

Patch like D116735 <https://reviews.llvm.org/D116735> suggest improvement for LSR, but we currently
don't have test coverage for this. This patch is copies the test cases
loop-strength-reduce*.ll from CodeGen/X86.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D123458

Files:
  llvm/test/CodeGen/X86/splat-for-size.ll


Index: llvm/test/CodeGen/X86/splat-for-size.ll
===================================================================
--- llvm/test/CodeGen/X86/splat-for-size.ll
+++ llvm/test/CodeGen/X86/splat-for-size.ll
@@ -388,9 +388,7 @@
 ; AVX-LABEL: pr23259:
 ; AVX:       # %bb.0: # %entry
 ; AVX-NEXT:    pushq $1
-; AVX-NEXT:    .cfi_adjust_cfa_offset 8
 ; AVX-NEXT:    popq %rax
-; AVX-NEXT:    .cfi_adjust_cfa_offset -8
 ; AVX-NEXT:    vmovq %rax, %xmm0
 ; AVX-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm1
 ; AVX-NEXT:    vperm2f128 {{.*#+}} ymm0 = mem[2,3],ymm0[0,1]
@@ -402,9 +400,7 @@
 ; AVX2:       # %bb.0: # %entry
 ; AVX2-NEXT:    vmovdqa A(%rip), %ymm0
 ; AVX2-NEXT:    pushq $1
-; AVX2-NEXT:    .cfi_adjust_cfa_offset 8
 ; AVX2-NEXT:    popq %rax
-; AVX2-NEXT:    .cfi_adjust_cfa_offset -8
 ; AVX2-NEXT:    vmovq %rax, %xmm1
 ; AVX2-NEXT:    vpunpcklqdq {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2]
 ; AVX2-NEXT:    vpermq {{.*#+}} ymm0 = ymm0[2,1,1,1]
@@ -417,8 +413,8 @@
   ret <8 x i64> %shuffle
 }
 
-attributes #0 = { optsize }
-attributes #1 = { minsize }
+attributes #0 = { nounwind optsize }
+attributes #1 = { nounwind minsize }
 
 !llvm.module.flags = !{!0}
 !0 = !{i32 1, !"ProfileSummary", !1}


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