[PATCH] D123366: [PowerPC] map hardware loop intrinsics to PowerPC pseudo instructions.

[ChenZheng via Phabricator via llvm-commits]

shchenz created this revision.
shchenz added reviewers: jsji, nemanjai, PowerPC.
Herald added subscribers: steven.zhang, kbarton, hiraditya.
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This is based on D122125 <https://reviews.llvm.org/D122125>. In D122125 <https://reviews.llvm.org/D122125>, we added a new post-isel pass to expand two new ctr loop pseudo instructions `MTCTR8Pseudo` and `DecreaseCTR8Pseudo`.

This patch maps hardware loop intrinsics loop_decrement and set_loop_iteration to the new PowerPC pseudo instructions, so that the hardware loop intrinsics will be expanded to normal cmp+branch form or ctrloop form based on the CTR register usage on MIR level.

We reuse legacy `MTCTR8loop` and update `DecreaseCTR8Pseudo` to `DecreaseCTR8loop` as well.

We still need another patch to remove the IR level CTR clobber check codes in PPCTargetTransformInfo.cpp


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D123366

Files:
  llvm/lib/Target/PowerPC/PPCCTRLoops.cpp
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/ctrloops32.mir
  llvm/test/CodeGen/PowerPC/ctrloops64.mir
  llvm/test/CodeGen/PowerPC/sms-phi.ll

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