[llvm] 3d4ca8a - [CSKY] Correct the alignment of FPR register

[Zi Xuan Wu via llvm-commits]

Author: Zi Xuan Wu
Date: 2022-04-08T14:37:07+08:00
New Revision: 3d4ca8a8c39f772dd6c022220a6eef23238a77f6

URL: https://github.com/llvm/llvm-project/commit/3d4ca8a8c39f772dd6c022220a6eef23238a77f6
DIFF: https://github.com/llvm/llvm-project/commit/3d4ca8a8c39f772dd6c022220a6eef23238a77f6.diff

LOG: [CSKY] Correct the alignment of FPR register

The alignment of FPR64 and sFPR64 declared in RegisterClass should be 32 bit.

Added: 
    

Modified: 
    llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp
    llvm/lib/Target/CSKY/CSKYRegisterInfo.td

Removed: 
    


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diff  --git a/llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp b/llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp
index f67147a60c61e..0d27187d444ed 100644
--- a/llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp
+++ b/llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp
@@ -1721,9 +1721,9 @@ unsigned CSKYAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
   if (CSKYMCRegisterClasses[CSKY::FPR32RegClassID].contains(Reg)) {
     // As the parser couldn't 
diff erentiate an FPR64 from an FPR32, coerce the
     // register from FPR32 to FPR64 if necessary.
-    if (Kind == MCK_FPR64 || Kind == MCK_sFPR64_V) {
+    if (Kind == MCK_FPR64 || Kind == MCK_sFPR64) {
       Op.Reg.RegNum = convertFPR32ToFPR64(Reg);
-      if (Kind == MCK_sFPR64_V &&
+      if (Kind == MCK_sFPR64 &&
           (Op.Reg.RegNum < CSKY::F0_64 || Op.Reg.RegNum > CSKY::F15_64))
         return Match_InvalidRegOutOfRange;
       if (Kind == MCK_FPR64 &&

diff  --git a/llvm/lib/Target/CSKY/CSKYRegisterInfo.td b/llvm/lib/Target/CSKY/CSKYRegisterInfo.td
index d72bf81829ec7..d12532a3c5c19 100644
--- a/llvm/lib/Target/CSKY/CSKYRegisterInfo.td
+++ b/llvm/lib/Target/CSKY/CSKYRegisterInfo.td
@@ -193,9 +193,9 @@ def FPR32 : RegisterClass<"CSKY", [f32], 32,
 def sFPR32 : RegisterClass<"CSKY", [f32], 32,
                          (add (sequence "F%u_32", 0, 15))>;
 
-def FPR64 : RegisterClass<"CSKY", [f64], 64,
+def FPR64 : RegisterClass<"CSKY", [f64], 32,
                          (add (sequence "F%u_64", 0, 31))>;
-def sFPR64 : RegisterClass<"CSKY", [f64], 64,
+def sFPR64 : RegisterClass<"CSKY", [f64], 32,
                          (add (sequence "F%u_64", 0, 15))>;
 
 def sFPR64_V : RegisterClass<"CSKY", [v2f32], 32, (add sFPR64)>;