[PATCH] D122951: [RISCV][SelectionDAG] Add a hook to sign extend i32 ConstantInt operands of phis on RV64.
Luís Marques via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 7 15:35:40 PDT 2022
luismarques added inline comments.
================
Comment at: llvm/test/CodeGen/RISCV/aext-to-sext.ll:81
+; SelectionDAGBuilder is zero extend we have a target hook to override it.
+define i64 @sext_phi_constnats(i32 %c) {
; RV64I-LABEL: miscompile:
----------------
jrtc27 wrote:
> Also marking %c as signext (which is what the psABI gives you) would avoid the sext.w noise
> Also marking %c as signext (which is what the psABI gives you) would avoid the sext.w noise
In external conversations, I've commented that IMO we should be using signext more extensively in the RISC-V tests (e.g. default to adding it to every parameter unless it doesn't actually make sense). I didn't seem to have managed to persuade my audience but, until I see further arguments against it, I still stand by my position :)
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https://reviews.llvm.org/D122951/new/
https://reviews.llvm.org/D122951
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