[PATCH] D123334: [BOLT] Update skipRelocation for aarch64

[Vladislav Khmelevsky via Phabricator via llvm-commits]

yota9 created this revision.
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The ld might relax ADRP+ADD or ADRP+LDR sequences to the ADR+NOP, add
the new case to the skipRelocation for aarch64.

Vladislav Khmelevsky,
Advanced Software Technology Lab, Huawei


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D123334

Files:
  bolt/lib/Core/Relocation.cpp
  bolt/test/runtime/plt-lld.test


Index: bolt/test/runtime/plt-lld.test
===================================================================
--- bolt/test/runtime/plt-lld.test
+++ bolt/test/runtime/plt-lld.test
@@ -1,9 +1,16 @@
 // This test checks that the pointers to PLT are properly updated.
 // The test is using lld linker.
 
-// RUN: %clang %cflags %p/../Inputs/plt.c -fuse-ld=lld \
-// RUN:    -o %t.lld.exe -Wl,-q
-// RUN: llvm-bolt %t.lld.exe -o %t.lld.bolt.exe -use-old-text=0 -lite=0
-// RUN: %t.lld.bolt.exe | FileCheck %s
+// Non-PIE:
+RUN: %clang %cflags -no-pie %p/../Inputs/plt.c -fuse-ld=lld \
+RUN:    -o %t.lld.exe -Wl,-q
+RUN: llvm-bolt %t.lld.exe -o %t.lld.bolt.exe -use-old-text=0 -lite=0
+RUN: %t.lld.bolt.exe | FileCheck %s
 
-// CHECK: Test completed
+// PIE:
+RUN: %clang %cflags -fPIC -pie %p/../Inputs/plt.c -fuse-ld=lld \
+RUN:    -o %t.lld.pie.exe -Wl,-q
+RUN: llvm-bolt %t.lld.pie.exe -o %t.lld.bolt.pie.exe -use-old-text=0 -lite=0
+RUN: %t.lld.bolt.pie.exe | FileCheck %s
+
+CHECK: Test completed
Index: bolt/lib/Core/Relocation.cpp
===================================================================
--- bolt/lib/Core/Relocation.cpp
+++ bolt/lib/Core/Relocation.cpp
@@ -168,16 +168,17 @@
 bool skipRelocationProcessAArch64(uint64_t Type, uint64_t Contents) {
   auto IsMov = [](uint64_t Contents) -> bool {
     // The bits 28-23 are 0b100101
-    if ((Contents & 0x1f800000) == 0x12800000)
-      return true;
-    return false;
+    return (Contents & 0x1f800000) == 0x12800000;
   };
 
   auto IsB = [](uint64_t Contents) -> bool {
     // The bits 31-26 are 0b000101
-    if ((Contents & 0xfc000000) == 0x14000000)
-      return true;
-    return false;
+    return (Contents & 0xfc000000) == 0x14000000;
+  };
+
+  auto IsAdr = [](uint64_t Contents) -> bool {
+    // The bits 31-24 are 0b0xx10000
+    return (Contents & 0x9f000000) == 0x10000000;
   };
 
   auto IsNop = [](uint64_t Contents) -> bool { return Contents == 0xd503201f; };
@@ -223,6 +224,18 @@
   }
   }
 
+  // The ld might relax ADRP+ADD or ADRP+LDR sequences to the ADR+NOP
+  switch (Type) {
+  default:
+    break;
+  case ELF::R_AARCH64_ADR_PREL_PG_HI21:
+  case ELF::R_AARCH64_ADD_ABS_LO12_NC:
+  case ELF::R_AARCH64_ADR_GOT_PAGE:
+  case ELF::R_AARCH64_LD64_GOT_LO12_NC:
+    if (IsAdr(Contents))
+      return true;
+  }
+
   return false;
 }
 


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