[llvm] afa1ae9 - [InstCombine] SimplifyDemandedUseBits - allow and(srem(X,Pow2),C) -> and(X,C) to work on vector types
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 7 07:25:01 PDT 2022
Author: Simon Pilgrim
Date: 2022-04-07T15:24:45+01:00
New Revision: afa1ae9e0c0bb7bacca65ebd43ecb21d3848bbe4
URL: https://github.com/llvm/llvm-project/commit/afa1ae9e0c0bb7bacca65ebd43ecb21d3848bbe4
DIFF: https://github.com/llvm/llvm-project/commit/afa1ae9e0c0bb7bacca65ebd43ecb21d3848bbe4.diff
LOG: [InstCombine] SimplifyDemandedUseBits - allow and(srem(X,Pow2),C) -> and(X,C) to work on vector types
Replace m_ConstantInt with m_APInt to match uniform (no-undef) vector remainder amounts.
Added:
Modified:
llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
llvm/test/Transforms/InstCombine/2008-07-11-RemAnd.ll
Removed:
################################################################################
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
index 96c59c79e4325..278db05f65d1b 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -739,13 +739,13 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
break;
}
case Instruction::SRem: {
- ConstantInt *Rem;
- if (match(I->getOperand(1), m_ConstantInt(Rem))) {
+ const APInt *Rem;
+ if (match(I->getOperand(1), m_APInt(Rem))) {
// X % -1 demands all the bits because we don't want to introduce
// INT_MIN % -1 (== undef) by accident.
- if (Rem->isMinusOne())
+ if (Rem->isAllOnes())
break;
- APInt RA = Rem->getValue().abs();
+ APInt RA = Rem->abs();
if (RA.isPowerOf2()) {
if (DemandedMask.ult(RA)) // srem won't affect demanded bits
return I->getOperand(0);
diff --git a/llvm/test/Transforms/InstCombine/2008-07-11-RemAnd.ll b/llvm/test/Transforms/InstCombine/2008-07-11-RemAnd.ll
index 67c489c054d01..0038abe5e7b11 100644
--- a/llvm/test/Transforms/InstCombine/2008-07-11-RemAnd.ll
+++ b/llvm/test/Transforms/InstCombine/2008-07-11-RemAnd.ll
@@ -17,9 +17,8 @@ entry:
define <2 x i32> @a_vec(<2 x i32> %b) nounwind {
; CHECK-LABEL: @a_vec(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = srem <2 x i32> [[B:%.*]], <i32 8, i32 8>
-; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[TMP0]], <i32 1, i32 1>
-; CHECK-NEXT: ret <2 x i32> [[TMP1]]
+; CHECK-NEXT: [[TMP0:%.*]] = and <2 x i32> [[B:%.*]], <i32 1, i32 1>
+; CHECK-NEXT: ret <2 x i32> [[TMP0]]
;
entry:
srem <2 x i32> %b, <i32 8, i32 8>
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