[PATCH] D76445: [RISCV][GlobalISel] Select ALU GPR instructions

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVGISel.td:30
+class PatSExtOpWGI<SDPatternOperator OpNode, RVInst Inst>
+    : Pat<(i64 (sra (shl (OpNode GPR:$rs1, GPR:$rs2), (i64 32)), (i64 32))),
+          (Inst GPR:$rs1, GPR:$rs2)>;
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lewis-revill wrote:
> arsenm wrote:
> > Should sext_inreg be legal?
> This is what I'm stuck on right now. It really should to match the SelectionDAG code, at least for i32 -> i64. However there is no way to map `G_SEXT_INREG` to `sext_inreg` because `sext_inreg` uses a value type as a DAG operand, whereas `G_SEXT_INREG` uses a constant which indicates the size of the original type. So no patterns defined which use `sext_inreg` will work for GlobalISel. I think my only option left is to do custom selection code.
You can either do custom selection code, or you could add support for sext_inreg in GlobalISelEmitter. It's a special case so it requires special support


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https://reviews.llvm.org/D76445