[llvm] ca3c746 - [LoongArch] Split asmstr to opcstr and opnstr in LAInst class definition. NFC
Weining Lu via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 7 04:36:30 PDT 2022
Author: Weining Lu
Date: 2022-04-07T19:16:51+08:00
New Revision: ca3c746ba818710a3945c880e745c4d5468c2581
URL: https://github.com/llvm/llvm-project/commit/ca3c746ba818710a3945c880e745c4d5468c2581
DIFF: https://github.com/llvm/llvm-project/commit/ca3c746ba818710a3945c880e745c4d5468c2581.diff
LOG: [LoongArch] Split asmstr to opcstr and opnstr in LAInst class definition. NFC
This change removes a lot of redundant strconcat usings.
Added:
Modified:
llvm/lib/Target/LoongArch/LoongArchInstrFormats.td
llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td b/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td
index 7c01776646e90..175a03e1d970d 100644
--- a/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td
+++ b/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td
@@ -16,7 +16,8 @@
//
//===----------------------------------------------------------------------===//
-class LAInst<dag outs, dag ins, string asmstr, list<dag> pattern = []>
+class LAInst<dag outs, dag ins, string opcstr, string opnstr,
+ list<dag> pattern = []>
: Instruction {
field bits<32> Inst;
// SoftFail is a field the disassembler can use to provide a way for
@@ -29,22 +30,23 @@ class LAInst<dag outs, dag ins, string asmstr, list<dag> pattern = []>
let Size = 4;
let OutOperandList = outs;
let InOperandList = ins;
- let AsmString = asmstr;
+ let AsmString = opcstr # "\t" # opnstr;
let Pattern = pattern;
}
// Pseudo instructions
-class Pseudo<dag outs, dag ins, list<dag> pattern = [], string asmstr = "">
- : LAInst<outs, ins, asmstr, pattern> {
+class Pseudo<dag outs, dag ins, list<dag> pattern = [], string opcstr = "",
+ string opnstr = "">
+ : LAInst<outs, ins, opcstr, opnstr, pattern> {
let isPseudo = 1;
let isCodeGenOnly = 1;
}
// 2R-type
// <opcode | rj | rd>
-class Fmt2R<bits<22> op, dag outs, dag ins, string asmstr,
+class Fmt2R<bits<22> op, dag outs, dag ins, string opcstr, string opnstr,
list<dag> pattern = []>
- : LAInst<outs, ins, asmstr, pattern> {
+ : LAInst<outs, ins, opcstr, opnstr, pattern> {
bits<5> rj;
bits<5> rd;
@@ -56,9 +58,9 @@ class Fmt2R<bits<22> op, dag outs, dag ins, string asmstr,
// 3R-type
// <opcode | rk | rj | rd>
// <opcode | fk | fj | fd>
-class Fmt3R<bits<17> op, dag outs, dag ins, string asmstr,
+class Fmt3R<bits<17> op, dag outs, dag ins, string opcstr, string opnstr,
list<dag> pattern = []>
- : LAInst<outs, ins, asmstr, pattern> {
+ : LAInst<outs, ins, opcstr, opnstr, pattern> {
bits<5> rk;
bits<5> rj;
bits<5> rd;
@@ -69,9 +71,9 @@ class Fmt3R<bits<17> op, dag outs, dag ins, string asmstr,
let Inst{4-0} = rd;
}
-class Fmt3FR<bits<17> op, dag outs, dag ins, string asmstr,
+class Fmt3FR<bits<17> op, dag outs, dag ins, string opcstr, string opnstr,
list<dag> pattern = []>
- : LAInst<outs, ins, asmstr, pattern> {
+ : LAInst<outs, ins, opcstr, opnstr, pattern> {
bits<5> fk;
bits<5> fj;
bits<5> fd;
@@ -84,9 +86,9 @@ class Fmt3FR<bits<17> op, dag outs, dag ins, string asmstr,
// 4R-type
// <opcode | ra | rk | rj | rd>
-class Fmt4R<bits<12> op, dag outs, dag ins, string asmstr,
+class Fmt4R<bits<12> op, dag outs, dag ins, string opcstr, string opnstr,
list<dag> pattern = []>
- : LAInst<outs, ins, asmstr, pattern> {
+ : LAInst<outs, ins, opcstr, opnstr, pattern> {
bits<5> ra;
bits<5> rk;
bits<5> rj;
@@ -101,9 +103,9 @@ class Fmt4R<bits<12> op, dag outs, dag ins, string asmstr,
// 3RI2-type
// <opcode | I2 | rk | rj | rd>
-class Fmt3RI2<bits<15> op, dag outs, dag ins, string asmstr,
+class Fmt3RI2<bits<15> op, dag outs, dag ins, string opcstr, string opnstr,
list<dag> pattern = []>
- : LAInst<outs, ins, asmstr, pattern> {
+ : LAInst<outs, ins, opcstr, opnstr, pattern> {
bits<2> imm2;
bits<5> rk;
bits<5> rj;
@@ -118,9 +120,9 @@ class Fmt3RI2<bits<15> op, dag outs, dag ins, string asmstr,
// 3RI3-type
// <opcode | I3 | rk | rj | rd>
-class Fmt3RI3<bits<14> op, dag outs, dag ins, string asmstr,
+class Fmt3RI3<bits<14> op, dag outs, dag ins, string opcstr, string opnstr,
list<dag> pattern = []>
- : LAInst<outs, ins, asmstr, pattern> {
+ : LAInst<outs, ins, opcstr, opnstr, pattern> {
bits<3> imm3;
bits<5> rk;
bits<5> rj;
@@ -135,9 +137,9 @@ class Fmt3RI3<bits<14> op, dag outs, dag ins, string asmstr,
// 2RI5-type
// <opcode | I5 | rj | rd>
-class Fmt2RI5<bits<17> op, dag outs, dag ins, string asmstr,
+class Fmt2RI5<bits<17> op, dag outs, dag ins, string opcstr, string opnstr,
list<dag> pattern = []>
- : LAInst<outs, ins, asmstr, pattern> {
+ : LAInst<outs, ins, opcstr, opnstr, pattern> {
bits<5> imm5;
bits<5> rj;
bits<5> rd;
@@ -150,9 +152,9 @@ class Fmt2RI5<bits<17> op, dag outs, dag ins, string asmstr,
// 2RI6-type
// <opcode | I6 | rj | rd>
-class Fmt2RI6<bits<16> op, dag outs, dag ins, string asmstr,
+class Fmt2RI6<bits<16> op, dag outs, dag ins, string opcstr, string opnstr,
list<dag> pattern = []>
- : LAInst<outs, ins, asmstr, pattern> {
+ : LAInst<outs, ins, opcstr, opnstr, pattern> {
bits<6> imm6;
bits<5> rj;
bits<5> rd;
@@ -165,9 +167,9 @@ class Fmt2RI6<bits<16> op, dag outs, dag ins, string asmstr,
// 2RI8-type
// <opcode | I8 | rj | rd>
-class Fmt2RI8<bits<14> op, dag outs, dag ins, string asmstr,
+class Fmt2RI8<bits<14> op, dag outs, dag ins, string opcstr, string opnstr,
list<dag> pattern = []>
- : LAInst<outs, ins, asmstr, pattern> {
+ : LAInst<outs, ins, opcstr, opnstr, pattern> {
bits<8> imm8;
bits<5> rj;
bits<5> rd;
@@ -180,9 +182,9 @@ class Fmt2RI8<bits<14> op, dag outs, dag ins, string asmstr,
// 2RI12-type
// <opcode | I12 | rj | rd>
-class Fmt2RI12<bits<10> op, dag outs, dag ins, string asmstr,
+class Fmt2RI12<bits<10> op, dag outs, dag ins, string opcstr, string opnstr,
list<dag> pattern = []>
- : LAInst<outs, ins, asmstr, pattern> {
+ : LAInst<outs, ins, opcstr, opnstr, pattern> {
bits<12> imm12;
bits<5> rj;
bits<5> rd;
@@ -195,9 +197,9 @@ class Fmt2RI12<bits<10> op, dag outs, dag ins, string asmstr,
// 2RI14-type
// <opcode | I14 | rj | rd>
-class Fmt2RI14<bits<8> op, dag outs, dag ins, string asmstr,
+class Fmt2RI14<bits<8> op, dag outs, dag ins, string opcstr, string opnstr,
list<dag> pattern = []>
- : LAInst<outs, ins, asmstr, pattern> {
+ : LAInst<outs, ins, opcstr, opnstr, pattern> {
bits<14> imm14;
bits<5> rj;
bits<5> rd;
@@ -210,9 +212,9 @@ class Fmt2RI14<bits<8> op, dag outs, dag ins, string asmstr,
// 2RI16-type
// <opcode | I16 | rj | rd>
-class Fmt2RI16<bits<6> op, dag outs, dag ins, string asmstr,
+class Fmt2RI16<bits<6> op, dag outs, dag ins, string opcstr, string opnstr,
list<dag> pattern = []>
- : LAInst<outs, ins, asmstr, pattern> {
+ : LAInst<outs, ins, opcstr, opnstr, pattern> {
bits<16> imm16;
bits<5> rj;
bits<5> rd;
@@ -225,9 +227,9 @@ class Fmt2RI16<bits<6> op, dag outs, dag ins, string asmstr,
// 1RI20-type
// <opcode | I20 | rd>
-class Fmt1RI20<bits<7> op, dag outs, dag ins, string asmstr,
+class Fmt1RI20<bits<7> op, dag outs, dag ins, string opcstr, string opnstr,
list<dag> pattern = []>
- : LAInst<outs, ins, asmstr, pattern> {
+ : LAInst<outs, ins, opcstr, opnstr, pattern> {
bits<20> imm20;
bits<5> rd;
@@ -238,9 +240,9 @@ class Fmt1RI20<bits<7> op, dag outs, dag ins, string asmstr,
// 1RI21-type
// <opcode | I21[15:0] | rj | I21[20:16]>
-class Fmt1RI21<bits<6> op, dag outs, dag ins, string asmstr,
+class Fmt1RI21<bits<6> op, dag outs, dag ins, string opcstr, string opnstr,
list<dag> pattern = []>
- : LAInst<outs, ins, asmstr, pattern> {
+ : LAInst<outs, ins, opcstr, opnstr, pattern> {
bits<21> imm21;
bits<5> rj;
@@ -252,9 +254,9 @@ class Fmt1RI21<bits<6> op, dag outs, dag ins, string asmstr,
// I15-type
// <opcode | I15>
-class FmtI15<bits<17> op, dag outs, dag ins, string asmstr,
+class FmtI15<bits<17> op, dag outs, dag ins, string opcstr, string opnstr,
list<dag> pattern = []>
- : LAInst<outs, ins, asmstr, pattern> {
+ : LAInst<outs, ins, opcstr, opnstr, pattern> {
bits<15> imm15;
let Inst{31-15} = op;
@@ -263,9 +265,9 @@ class FmtI15<bits<17> op, dag outs, dag ins, string asmstr,
// I26-type
// <opcode | I26[15:0] | I26[25:16]>
-class FmtI26<bits<6> op, dag outs, dag ins, string asmstr,
+class FmtI26<bits<6> op, dag outs, dag ins, string opcstr, string opnstr,
list<dag> pattern = []>
- : LAInst<outs, ins, asmstr, pattern> {
+ : LAInst<outs, ins, opcstr, opnstr, pattern> {
bits<26> imm26;
let Inst{31-26} = op;
@@ -275,9 +277,9 @@ class FmtI26<bits<6> op, dag outs, dag ins, string asmstr,
// FmtBSTR_W
// <opcode[11:1] | msbw | opcode[0] | lsbw | rj | rd>
-class FmtBSTR_W<bits<12> op, dag outs, dag ins, string asmstr,
+class FmtBSTR_W<bits<12> op, dag outs, dag ins, string opcstr, string opnstr,
list<dag> pattern = []>
- : LAInst<outs, ins, asmstr, pattern> {
+ : LAInst<outs, ins, opcstr, opnstr, pattern> {
bits<5> msbw;
bits<5> lsbw;
bits<5> rj;
@@ -293,9 +295,9 @@ class FmtBSTR_W<bits<12> op, dag outs, dag ins, string asmstr,
// FmtBSTR_D
// <opcode | msbd | lsbd | rj | rd>
-class FmtBSTR_D<bits<10> op, dag outs, dag ins, string asmstr,
+class FmtBSTR_D<bits<10> op, dag outs, dag ins, string opcstr, string opnstr,
list<dag> pattern = []>
- : LAInst<outs, ins, asmstr, pattern> {
+ : LAInst<outs, ins, opcstr, opnstr, pattern> {
bits<6> msbd;
bits<6> lsbd;
bits<5> rj;
@@ -310,9 +312,9 @@ class FmtBSTR_D<bits<10> op, dag outs, dag ins, string asmstr,
// FmtASRT
// <opcode | rk | rj | 0x0>
-class FmtASRT<bits<17> op, dag outs, dag ins, string asmstr,
+class FmtASRT<bits<17> op, dag outs, dag ins, string opcstr, string opnstr,
list<dag> pattern = []>
- : LAInst<outs, ins, asmstr, pattern> {
+ : LAInst<outs, ins, opcstr, opnstr, pattern> {
bits<5> rk;
bits<5> rj;
@@ -324,9 +326,9 @@ class FmtASRT<bits<17> op, dag outs, dag ins, string asmstr,
// FmtPRELD
// < 0b0010101011 | I12 | rj | I5>
-class FmtPRELD<dag outs, dag ins, string asmstr,
+class FmtPRELD<dag outs, dag ins, string opcstr, string opnstr,
list<dag> pattern = []>
- : LAInst<outs, ins, asmstr, pattern> {
+ : LAInst<outs, ins, opcstr, opnstr, pattern> {
bits<12> imm12;
bits<5> rj;
bits<5> imm5;
@@ -339,9 +341,9 @@ class FmtPRELD<dag outs, dag ins, string asmstr,
// FmtPRELDX
// < 0b00111000001011000 | rk | rj | I5>
-class FmtPRELDX<dag outs, dag ins, string asmstr,
+class FmtPRELDX<dag outs, dag ins, string opcstr, string opnstr,
list<dag> pattern = []>
- : LAInst<outs, ins, asmstr, pattern> {
+ : LAInst<outs, ins, opcstr, opnstr, pattern> {
bits<5> rk;
bits<5> rj;
bits<5> imm5;
diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
index 755e4389d839e..e718ebe9db3b1 100644
--- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
@@ -116,98 +116,91 @@ include "LoongArchInstrFormats.td"
// Instruction Class Templates
//===----------------------------------------------------------------------===//
class ALU_3R<bits<17> op, string opstr>
- : Fmt3R<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk),
- !strconcat(opstr, "\t$rd, $rj, $rk")>;
+ : Fmt3R<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk), opstr, "$rd, $rj, $rk">;
class ALU_2R<bits<22> op, string opstr>
- : Fmt2R<op, (outs GPR:$rd), (ins GPR:$rj),
- !strconcat(opstr, "\t$rd, $rj")>;
+ : Fmt2R<op, (outs GPR:$rd), (ins GPR:$rj), opstr, "$rd, $rj">;
class ALU_3RI2<bits<15> op, string opstr, Operand ImmOpnd>
- : Fmt3RI2<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk, ImmOpnd:$imm2),
- !strconcat(opstr, "\t$rd, $rj, $rk, $imm2")>;
+ : Fmt3RI2<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk, ImmOpnd:$imm2), opstr,
+ "$rd, $rj, $rk, $imm2">;
class ALU_3RI3<bits<14> op, string opstr, Operand ImmOpnd>
- : Fmt3RI3<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk, ImmOpnd:$imm3),
- !strconcat(opstr, "\t$rd, $rj, $rk, $imm3")>;
+ : Fmt3RI3<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk, ImmOpnd:$imm3), opstr,
+ "$rd, $rj, $rk, $imm3">;
class ALU_2RI5<bits<17> op, string opstr, Operand ImmOpnd>
- : Fmt2RI5<op, (outs GPR:$rd), (ins GPR:$rj, ImmOpnd:$imm5),
- !strconcat(opstr, "\t$rd, $rj, $imm5")>;
+ : Fmt2RI5<op, (outs GPR:$rd), (ins GPR:$rj, ImmOpnd:$imm5), opstr,
+ "$rd, $rj, $imm5">;
class ALU_2RI6<bits<16> op, string opstr, Operand ImmOpnd>
- : Fmt2RI6<op, (outs GPR:$rd), (ins GPR:$rj, ImmOpnd:$imm6),
- !strconcat(opstr, "\t$rd, $rj, $imm6")>;
+ : Fmt2RI6<op, (outs GPR:$rd), (ins GPR:$rj, ImmOpnd:$imm6), opstr,
+ "$rd, $rj, $imm6">;
class ALU_2RI12<bits<10> op, string opstr, Operand ImmOpnd>
- : Fmt2RI12<op, (outs GPR:$rd), (ins GPR:$rj, ImmOpnd:$imm12),
- !strconcat(opstr, "\t$rd, $rj, $imm12")>;
+ : Fmt2RI12<op, (outs GPR:$rd), (ins GPR:$rj, ImmOpnd:$imm12), opstr,
+ "$rd, $rj, $imm12">;
class ALU_2RI16<bits<6> op, string opstr, Operand ImmOpnd>
- : Fmt2RI16<op, (outs GPR:$rd), (ins GPR:$rj, ImmOpnd:$imm16),
- !strconcat(opstr, "\t$rd, $rj, $imm16")>;
+ : Fmt2RI16<op, (outs GPR:$rd), (ins GPR:$rj, ImmOpnd:$imm16), opstr,
+ "$rd, $rj, $imm16">;
class ALU_1RI20<bits<7> op, string opstr, Operand ImmOpnd>
- : Fmt1RI20<op, (outs GPR:$rd), (ins ImmOpnd:$imm20),
- !strconcat(opstr, "\t$rd, $imm20")>;
+ : Fmt1RI20<op, (outs GPR:$rd), (ins ImmOpnd:$imm20), opstr, "$rd, $imm20">;
class MISC_I15<bits<17> op, string opstr>
- : FmtI15<op, (outs), (ins uimm15:$imm15), !strconcat(opstr, "\t$imm15")>;
+ : FmtI15<op, (outs), (ins uimm15:$imm15), opstr, "$imm15">;
class RDTIME_2R<bits<22> op, string opstr>
- : Fmt2R<op, (outs GPR:$rd, GPR:$rj), (ins),
- !strconcat(opstr, "\t$rd, $rj")>;
+ : Fmt2R<op, (outs GPR:$rd, GPR:$rj), (ins), opstr, "$rd, $rj">;
class BrCC_2RI16<bits<6> op, string opstr>
- : Fmt2RI16<op, (outs), (ins GPR:$rj, GPR:$rd, simm16_lsl2:$imm16),
- !strconcat(opstr, "\t$rj, $rd, $imm16")> {
+ : Fmt2RI16<op, (outs), (ins GPR:$rj, GPR:$rd, simm16_lsl2:$imm16), opstr,
+ "$rj, $rd, $imm16"> {
let isBranch = 1;
let isTerminator = 1;
}
class BrCCZ_1RI21<bits<6> op, string opstr>
- : Fmt1RI21<op, (outs), (ins GPR:$rj, simm21_lsl2:$imm21),
- !strconcat(opstr, "\t$rj, $imm21")> {
+ : Fmt1RI21<op, (outs), (ins GPR:$rj, simm21_lsl2:$imm21), opstr,
+ "$rj, $imm21"> {
let isBranch = 1;
let isTerminator = 1;
}
class Br_I26<bits<6> op, string opstr>
- : FmtI26<op, (outs), (ins simm26_lsl2:$imm26),
- !strconcat(opstr, "\t$imm26")> {
+ : FmtI26<op, (outs), (ins simm26_lsl2:$imm26), opstr, "$imm26"> {
let isBranch = 1;
let isTerminator = 1;
}
let mayLoad = 1 in {
class LOAD_3R<bits<17> op, string opstr>
- : Fmt3R<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk),
- !strconcat(opstr, "\t$rd, $rj, $rk")>;
+ : Fmt3R<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk), opstr, "$rd, $rj, $rk">;
class LOAD_2RI12<bits<10> op, string opstr>
- : Fmt2RI12<op, (outs GPR:$rd), (ins GPR:$rj, simm12:$imm12),
- !strconcat(opstr, "\t$rd, $rj, $imm12")>;
+ : Fmt2RI12<op, (outs GPR:$rd), (ins GPR:$rj, simm12:$imm12), opstr,
+ "$rd, $rj, $imm12">;
class LOAD_2RI14<bits<8> op, string opstr>
- : Fmt2RI14<op, (outs GPR:$rd), (ins GPR:$rj, simm14_lsl2:$imm14),
- !strconcat(opstr, "\t$rd, $rj, $imm14")>;
+ : Fmt2RI14<op, (outs GPR:$rd), (ins GPR:$rj, simm14_lsl2:$imm14), opstr,
+ "$rd, $rj, $imm14">;
} // mayLoad = 1
let mayStore = 1 in {
class STORE_3R<bits<17> op, string opstr>
- : Fmt3R<op, (outs), (ins GPR:$rd, GPR:$rj, GPR:$rk),
- !strconcat(opstr, "\t$rd, $rj, $rk")>;
+ : Fmt3R<op, (outs), (ins GPR:$rd, GPR:$rj, GPR:$rk), opstr,
+ "$rd, $rj, $rk">;
class STORE_2RI12<bits<10> op, string opstr>
- : Fmt2RI12<op, (outs), (ins GPR:$rd, GPR:$rj, simm12:$imm12),
- !strconcat(opstr, "\t$rd, $rj, $imm12")>;
+ : Fmt2RI12<op, (outs), (ins GPR:$rd, GPR:$rj, simm12:$imm12), opstr,
+ "$rd, $rj, $imm12">;
class STORE_2RI14<bits<8> op, string opstr>
- : Fmt2RI14<op, (outs), (ins GPR:$rd, GPR:$rj, simm14_lsl2:$imm14),
- !strconcat(opstr, "\t$rd, $rj, $imm14")>;
+ : Fmt2RI14<op, (outs), (ins GPR:$rd, GPR:$rj, simm14_lsl2:$imm14), opstr,
+ "$rd, $rj, $imm14">;
} // mayStore = 1
let mayLoad = 1, mayStore = 1 in
class AM_3R<bits<17> op, string opstr>
- : Fmt3R<op, (outs GPR:$rd), (ins GPR:$rk, GPR:$rj),
- !strconcat(opstr, "\t$rd, $rk, $rj")>;
+ : Fmt3R<op, (outs GPR:$rd), (ins GPR:$rk, GPR:$rj), opstr, "$rd, $rk, $rj">;
let mayLoad = 1 in
class LLBase<bits<8> op, string opstr>
- : Fmt2RI14<op, (outs GPR:$rd), (ins GPR:$rj, simm14_lsl2:$imm14),
- !strconcat(opstr, "\t$rd, $rj, $imm14")>;
+ : Fmt2RI14<op, (outs GPR:$rd), (ins GPR:$rj, simm14_lsl2:$imm14), opstr,
+ "$rd, $rj, $imm14">;
let mayStore = 1, Constraints = "$rd = $dst" in
class SCBase<bits<8> op, string opstr>
: Fmt2RI14<op, (outs GPR:$dst), (ins GPR:$rd, GPR:$rj, simm14_lsl2:$imm14),
- !strconcat(opstr, "\t$rd, $rj, $imm14")>;
+ opstr, "$rd, $rj, $imm14">;
//===----------------------------------------------------------------------===//
// Instructions
@@ -268,11 +261,11 @@ def BITREV_W : ALU_2R<0b0000000000000000010100, "bitrev.w">;
let Constraints = "$rd = $dst" in {
def BSTRINS_W : FmtBSTR_W<0b000000000110, (outs GPR:$dst),
(ins GPR:$rd, GPR:$rj, uimm5:$msbw, uimm5:$lsbw),
- "bstrins.w\t$rd, $rj, $msbw, $lsbw">;
+ "bstrins.w", "$rd, $rj, $msbw, $lsbw">;
}
def BSTRPICK_W : FmtBSTR_W<0b000000000111, (outs GPR:$rd),
(ins GPR:$rj, uimm5:$msbw, uimm5:$lsbw),
- "bstrpick.w\t$rd, $rj, $msbw, $lsbw">;
+ "bstrpick.w", "$rd, $rj, $msbw, $lsbw">;
def MASKEQZ : ALU_3R<0b00000000000100110, "maskeqz">;
def MASKNEZ : ALU_3R<0b00000000000100111, "masknez">;
@@ -288,10 +281,10 @@ def BNEZ : BrCCZ_1RI21<0b010001, "bnez">;
def B : Br_I26<0b010100, "b">;
let isCall = 1 in
-def BL : FmtI26<0b010101, (outs), (ins simm26_lsl2:$imm26), "bl\t$imm26">;
+def BL : FmtI26<0b010101, (outs), (ins simm26_lsl2:$imm26), "bl", "$imm26">;
def JIRL : Fmt2RI16<0b010011, (outs GPR:$rd),
- (ins GPR:$rj, simm16_lsl2:$imm16),
- "jirl\t$rd, $rj, $imm16">;
+ (ins GPR:$rj, simm16_lsl2:$imm16), "jirl",
+ "$rd, $rj, $imm16">;
// Common Memory Access Instructions
def LD_B : LOAD_2RI12<0b0010100000, "ld.b">;
@@ -302,8 +295,8 @@ def LD_HU : LOAD_2RI12<0b0010101001, "ld.hu">;
def ST_B : STORE_2RI12<0b0010100100, "st.b">;
def ST_H : STORE_2RI12<0b0010100101, "st.h">;
def ST_W : STORE_2RI12<0b0010100110, "st.w">;
-def PRELD : FmtPRELD<(outs), (ins uimm5:$imm5, GPR:$rj, simm12:$imm12),
- "preld\t$imm5, $rj, $imm12">;
+def PRELD : FmtPRELD<(outs), (ins uimm5:$imm5, GPR:$rj, simm12:$imm12), "preld",
+ "$imm5, $rj, $imm12">;
// Atomic Memory Access Instructions
def LL_W : LLBase<0b00100000, "ll.w">;
@@ -333,8 +326,8 @@ def ALSL_WU : ALU_3RI2<0b000000000000011, "alsl.wu", uimm2_plus1>;
def ALSL_D : ALU_3RI2<0b000000000010110, "alsl.d", uimm2_plus1>;
let Constraints = "$rd = $dst" in {
def LU32I_D : Fmt1RI20<0b0001011, (outs GPR:$dst),
- (ins GPR:$rd, simm20:$imm20),
- "lu32i.d\t$rd, $imm20">;
+ (ins GPR:$rd, simm20:$imm20), "lu32i.d",
+ "$rd, $imm20">;
}
def LU52I_D : ALU_2RI12<0b0000001100, "lu52i.d", simm12>;
def PCADDU18I : ALU_1RI20<0b0001111, "pcaddu18i", simm20>;
@@ -374,11 +367,11 @@ def BITREV_D : ALU_2R<0b0000000000000000010101, "bitrev.d">;
let Constraints = "$rd = $dst" in {
def BSTRINS_D : FmtBSTR_D<0b0000000010, (outs GPR:$dst),
(ins GPR:$rd, GPR:$rj, uimm6:$msbd, uimm6:$lsbd),
- "bstrins.d\t$rd, $rj, $msbd, $lsbd">;
+ "bstrins.d", "$rd, $rj, $msbd, $lsbd">;
}
def BSTRPICK_D : FmtBSTR_D<0b0000000011, (outs GPR:$rd),
(ins GPR:$rj, uimm6:$msbd, uimm6:$lsbd),
- "bstrpick.d\t$rd, $rj, $msbd, $lsbd">;
+ "bstrpick.d", "$rd, $rj, $msbd, $lsbd">;
// Common Memory Access Instructions for 64-bits
def LD_WU : LOAD_2RI12<0b0010101010, "ld.wu">;
@@ -398,8 +391,8 @@ def LDPTR_W : LOAD_2RI14<0b00100100, "ldptr.w">;
def LDPTR_D : LOAD_2RI14<0b00100110, "ldptr.d">;
def STPTR_W : STORE_2RI14<0b00100101, "stptr.w">;
def STPTR_D : STORE_2RI14<0b00100111, "stptr.d">;
-def PRELDX : FmtPRELDX<(outs), (ins uimm5:$imm5, GPR:$rj, GPR:$rk),
- "preldx\t$imm5, $rj, $rk">;
+def PRELDX : FmtPRELDX<(outs), (ins uimm5:$imm5, GPR:$rj, GPR:$rk), "preldx",
+ "$imm5, $rj, $rk">;
// Bound Check Memory Access Instructions
def LDGT_B : LOAD_3R<0b00111000011110000, "ldgt.b">;
@@ -471,9 +464,9 @@ def CRCC_W_D_W : ALU_3R<0b00000000001001111, "crcc.w.d.w">;
// Other Miscellaneous Instructions for 64-bits
def ASRTLE_D : FmtASRT<0b00000000000000010, (outs), (ins GPR:$rj, GPR:$rk),
- "asrtle.d\t$rj, $rk">;
+ "asrtle.d", "$rj, $rk">;
def ASRTGT_D : FmtASRT<0b00000000000000011, (outs), (ins GPR:$rj, GPR:$rk),
- "asrtgt.d\t$rj, $rk">;
+ "asrtgt.d", "$rj, $rk">;
def RDTIME_D : RDTIME_2R<0b0000000000000000011010, "rdtime.d">;
} // Predicates = [IsLA64]
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