[llvm] 8ebc9b1 - [RISCV] Select unmasked integer setcc insts via ISel post-process
Fraser Cormack via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 7 01:41:54 PDT 2022
Author: Fraser Cormack
Date: 2022-04-07T09:30:19+01:00
New Revision: 8ebc9b1560655836aa6cdf86e9fcecea6ab62730
URL: https://github.com/llvm/llvm-project/commit/8ebc9b1560655836aa6cdf86e9fcecea6ab62730
DIFF: https://github.com/llvm/llvm-project/commit/8ebc9b1560655836aa6cdf86e9fcecea6ab62730.diff
LOG: [RISCV] Select unmasked integer setcc insts via ISel post-process
This patch has no effect on the generated code, whilst mitigating the
increase in ISel table size caused by the recent addition of masked
patterns.
I aim to do the same for floating-point patterns once D123051 lands,
giving us a reason to use masked floating-point patterns.
Reviewed By: arcbbb
Differential Revision: https://reviews.llvm.org/D123217
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index c2c04add5e0b6..dfcfa3cf9d571 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -1769,7 +1769,8 @@ multiclass VPseudoBinaryM<VReg RetClass,
Constraint>;
let ForceTailAgnostic = true in
def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMOutMask<RetClass, Op1Class,
- Op2Class, Constraint>;
+ Op2Class, Constraint>,
+ RISCVMaskedPseudo</*MaskOpIdx*/ 3>;
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 6d0ce41ab3bdd..7367140df8279 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -451,13 +451,6 @@ multiclass VPatBinaryFPVL_R_VF<SDNode vop, string instruction_name> {
multiclass VPatIntegerSetCCVL_VV<VTypeInfo vti, string instruction_name,
CondCode cc> {
- def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
- vti.RegClass:$rs2, cc,
- (vti.Mask true_mask),
- VLOpFrag)),
- (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
- vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl,
- vti.Log2SEW)>;
def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
vti.RegClass:$rs2, cc,
(vti.Mask V0),
@@ -473,13 +466,6 @@ multiclass VPatIntegerSetCCVL_VV<VTypeInfo vti, string instruction_name,
multiclass VPatIntegerSetCCVL_VV_Swappable<VTypeInfo vti, string instruction_name,
CondCode cc, CondCode invcc> :
VPatIntegerSetCCVL_VV<vti, instruction_name, cc> {
- def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs2),
- vti.RegClass:$rs1, invcc,
- (vti.Mask true_mask),
- VLOpFrag)),
- (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
- vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl,
- vti.Log2SEW)>;
def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs2),
vti.RegClass:$rs1, invcc,
(vti.Mask V0),
@@ -491,24 +477,13 @@ multiclass VPatIntegerSetCCVL_VV_Swappable<VTypeInfo vti, string instruction_nam
multiclass VPatIntegerSetCCVL_VX_Swappable<VTypeInfo vti, string instruction_name,
CondCode cc, CondCode invcc> {
- defvar instruction = !cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX);
defvar instruction_masked = !cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX#"_MASK");
- def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
- (SplatPat (XLenVT GPR:$rs2)), cc,
- (vti.Mask true_mask),
- VLOpFrag)),
- (instruction vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>;
def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
(SplatPat (XLenVT GPR:$rs2)), cc,
(vti.Mask V0),
VLOpFrag)),
(instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1,
GPR:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>;
- def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat (XLenVT GPR:$rs2)),
- (vti.Vector vti.RegClass:$rs1), invcc,
- (vti.Mask true_mask),
- VLOpFrag)),
- (instruction vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>;
def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat (XLenVT GPR:$rs2)),
(vti.Vector vti.RegClass:$rs1), invcc,
(vti.Mask V0),
@@ -519,13 +494,7 @@ multiclass VPatIntegerSetCCVL_VX_Swappable<VTypeInfo vti, string instruction_nam
multiclass VPatIntegerSetCCVL_VI_Swappable<VTypeInfo vti, string instruction_name,
CondCode cc, CondCode invcc> {
- defvar instruction = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX);
defvar instruction_masked = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX#"_MASK");
- def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
- (SplatPat_simm5 simm5:$rs2), cc,
- (vti.Mask true_mask),
- VLOpFrag)),
- (instruction vti.RegClass:$rs1, XLenVT:$rs2, GPR:$vl, vti.Log2SEW)>;
def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
(SplatPat_simm5 simm5:$rs2), cc,
(vti.Mask V0),
@@ -533,11 +502,6 @@ multiclass VPatIntegerSetCCVL_VI_Swappable<VTypeInfo vti, string instruction_nam
(instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1,
XLenVT:$rs2, (vti.Mask V0), GPR:$vl,
vti.Log2SEW)>;
- def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat_simm5 simm5:$rs2),
- (vti.Vector vti.RegClass:$rs1), invcc,
- (vti.Mask true_mask),
- VLOpFrag)),
- (instruction vti.RegClass:$rs1, simm5:$rs2, GPR:$vl, vti.Log2SEW)>;
def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat_simm5 simm5:$rs2),
(vti.Vector vti.RegClass:$rs1), invcc,
(vti.Mask V0),
@@ -549,14 +513,7 @@ multiclass VPatIntegerSetCCVL_VI_Swappable<VTypeInfo vti, string instruction_nam
multiclass VPatIntegerSetCCVL_VIPlus1<VTypeInfo vti, string instruction_name,
CondCode cc, ComplexPattern splatpat_kind> {
- defvar instruction = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX);
defvar instruction_masked = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX#"_MASK");
- def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
- (splatpat_kind simm5:$rs2), cc,
- (vti.Mask true_mask),
- VLOpFrag)),
- (instruction vti.RegClass:$rs1, (DecImm simm5:$rs2),
- GPR:$vl, vti.Log2SEW)>;
def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
(splatpat_kind simm5:$rs2), cc,
(vti.Mask V0),
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