[PATCH] D122875: [DAGCombiner] Scalarize extend/truncate for splat vector.

Jianjian Guan via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Apr 6 23:40:09 PDT 2022


jacquesguan added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:437
     SDValue visitXOR(SDNode *N);
+    SDValue SimplifyVUnOp(SDNode *N, const SDLoc &DL);
     SDValue SimplifyVBinOp(SDNode *N, const SDLoc &DL);
----------------
craig.topper wrote:
> I don't think UnOp is the right term here. UnaryOperator in IR is the base clang used by fneg. CastOp would probably be better.
Done, thanks.


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Comment at: llvm/test/CodeGen/RISCV/rvv/vfwmacc-sdnode.ll:28
+; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vfmacc.vf v8, ft0, v10
 ; CHECK-NEXT:    ret
----------------
RKSimon wrote:
> Any luck with these regressions?
Done, thanks.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/vwsub-sdnode.ll:3
 ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
 
----------------
RKSimon wrote:
> You need to re-add triple specific checks now that some of these test results diverge
> ```
> ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK32
> ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK64
> ```
Done, thanks.


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D122875



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