[PATCH] D123180: [RISCV] Fixing stack offset for RVV object with vararg in stack.
Kito Cheng via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 6 20:44:24 PDT 2022
kito-cheng updated this revision to Diff 421079.
kito-cheng added a comment.
Changes:
- Move test case into test/CodeGen/RISCV/rvv.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D123180/new/
https://reviews.llvm.org/D123180
Files:
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir
Index: llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir
+++ llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir
@@ -164,7 +164,7 @@
; CHECK-NEXT: SD killed renamable $x16, killed $x10, 48 :: (store (s64) into %fixed-stack.1, align 16)
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 69, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: renamable $v8 = PseudoVMV_V_I_MF8 0, 2, 3, implicit $vl, implicit $vtype
- ; CHECK-NEXT: $x10 = ADDI $x2, 40
+ ; CHECK-NEXT: $x10 = ADDI $x2, 24
; CHECK-NEXT: PseudoVSPILL_M1 killed renamable $v8, killed $x10 :: (store unknown-size into %stack.1, align 8)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.while.cond:
@@ -179,7 +179,7 @@
; CHECK-NEXT: liveins: $x8, $x9
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 69, implicit-def $vl, implicit-def $vtype
- ; CHECK-NEXT: $x10 = ADDI $x2, 40
+ ; CHECK-NEXT: $x10 = ADDI $x2, 24
; CHECK-NEXT: renamable $v8 = PseudoVRELOAD_M1 killed $x10 :: (load unknown-size from %stack.1, align 8)
; CHECK-NEXT: PseudoVSE8_V_MF8 killed renamable $v8, renamable $x8, 2, 3, implicit $vl, implicit $vtype :: (store (s16) into %ir.0, align 1)
; CHECK-NEXT: $x10 = COPY renamable $x9
Index: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -674,7 +674,10 @@
if (hasBP(MF)) {
FrameReg = RISCVABI::getBPReg();
// |--------------------------| -- <-- FP
- // | callee-saved registers | | <----.
+ // | callee-allocated save | | <----|
+ // | area for register varargs| | |
+ // |--------------------------| | |
+ // | callee-saved registers | | |
// |--------------------------| -- |
// | realignment (the size of | | |
// | this area is not counted | | |
@@ -699,7 +702,10 @@
} else {
FrameReg = RISCV::X2;
// |--------------------------| -- <-- FP
- // | callee-saved registers | | <----.
+ // | callee-allocated save | | <----|
+ // | area for register varargs| | |
+ // |--------------------------| | |
+ // | callee-saved registers | | |
// |--------------------------| -- |
// | realignment (the size of | | |
// | this area is not counted | | |
@@ -742,6 +748,9 @@
// the frame size.
//
// |--------------------------| -- <-- FP
+ // | callee-allocated save | |
+ // | area for register varargs| |
+ // |--------------------------| |
// | callee-saved registers | |
// |--------------------------| | MFI.getStackSize()
// | scalar local variables | |
@@ -756,7 +765,10 @@
// When using SP to access frame objects, we need to add RVV stack size.
//
// |--------------------------| -- <-- FP
- // | callee-saved registers | | <----.
+ // | callee-allocated save | | <----|
+ // | area for register varargs| | |
+ // |--------------------------| | |
+ // | callee-saved registers | | |
// |--------------------------| -- |
// | Padding after RVV | | |
// | (not counted in | | |
@@ -786,8 +798,11 @@
Offset += StackOffset::getFixed(MFI.getStackSize());
}
} else if (MFI.getStackID(FI) == TargetStackID::ScalableVector) {
+ int ScalarLocalVarSize = MFI.getStackSize() -
+ RVFI->getCalleeSavedStackSize() -
+ RVFI->getVarArgsSaveSize();
Offset += StackOffset::get(
- alignTo(MFI.getStackSize() - RVFI->getCalleeSavedStackSize(), 8),
+ alignTo(ScalarLocalVarSize, 8),
RVFI->getRVVStackSize());
}
}
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