[PATCH] D123265: [RISCV] Extend the Merge Base Offset pass to handle AUIPC+ADDI

[Luís Marques via Phabricator via llvm-commits]

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Builds upon D123264 <https://reviews.llvm.org/D123264>, adding support to merge the low part of the LLA address into the load/store instruction offsets.

This needs more testing and more tests. But the priority is reviewing D123264 <https://reviews.llvm.org/D123264>, to clarify if this is even a viable approach.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D123265

Files:
  llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
  llvm/test/CodeGen/RISCV/codemodel-lowering.ll
  llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll

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