[PATCH] D123264: [RISCV] Pre-RA expand pseudos pass

[Luís Marques via Phabricator via llvm-commits]

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As discussed before, we aren't optimizing the LLA+Load/Stores (i.e. AUIPC+ADDI+Load/Stores) instruction sequences that we get with medany because:

- the pseudo instruction expansion pass runs late (in premit2, i.e. post-ra);
- the pass to merge the offset of address calculations into the offset of load/stores runs pre-ra, in SSA form.

Ideally, we want to expand the LLA pseudo instruction earlier and extend the offset folding pass to handle the AUIPC case. This patch implements that earlier expansion.

Just doing the same expansion we were doing but earlier, with virtual registers, runs into problems. It's easy for optimizations to separate the AUIPC instruction from the label of the BB that should point to the AUIPC.

- Earlier passes don't know about `LabelMustBeEmitted`. Originally I solved that by making that flag also imply `AddressTaken`. But creating BBs earlier was messing with various optimizations, so I ended up going for an implementation based on `createTempSymbol` + `setPreInstrSymbol`.

- The change to `MachineInstr::isPosition` to check `setPreInstrSymbol` was also needed for the same reason of avoiding breaking references to the AUIPC/%pcrel_hi.

- Although I haven't run into that problem, I think it's still possible for an ADDI to become out of range of the AUIPC it refers to, if other passes move them too far apart. For branches we have the branch relaxation pass to solve essentially the same problem. Are we going to need a similar pass for AUIPC/ADDI? Or can we prevent this from happening?


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D123264

Files:
  llvm/include/llvm/CodeGen/MachineInstr.h
  llvm/lib/Target/RISCV/RISCV.h
  llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
  llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/CodeGen/RISCV/O3-pipeline.ll
  llvm/test/CodeGen/RISCV/codemodel-lowering.ll
  llvm/test/CodeGen/RISCV/elf-preemption.ll
  llvm/test/CodeGen/RISCV/jumptable.ll
  llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll
  llvm/test/CodeGen/RISCV/mir-target-flags-medium.ll
  llvm/test/CodeGen/RISCV/mir-target-flags-small.ll
  llvm/test/CodeGen/RISCV/mir-target-flags.ll
  llvm/test/CodeGen/RISCV/pic-models.ll

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