[PATCH] D123255: [RISCV] Add more .vx patterns for VLMax integer setccs.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll:53
 ; RV32D-NEXT:    vsetvli a0, zero, e8, mf8, ta, mu
-; RV32D-NEXT:    vmv.v.i v9, 0
-; RV32D-NEXT:    vmseq.vv v0, v9, v8
+; RV32D-NEXT:    vmseq.vx v0, v8, zero
 ; RV32D-NEXT:    vrsub.vi v9, v8, 0
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This was bad canonicalization of a splat with 0 which should stay on the RHS. I've posted D123256 to fix the canonicalization.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D123255/new/

https://reviews.llvm.org/D123255